Time to market matters but if you can not debug your design then how quickly you got to gates does not matter one iota. Software development tools permit straight forward debugging techniques. Not so with logic designs, and especially not ones from C/C++ which actually make the problem 10-100 times worse!
2 posts • joined 2 Oct 2019
Hate Verilog? Detest VHDL? You're not the only one. Xilinx rolls out easier-to-use free FPGA programming tools after developer outcry
Re: Might be a long time before I use it
My experience so far working with HLS and P4 is that Xilinx tools crank out the code very quickly for the result but it is close to impossible to debug what is going wrong with out months of guess work. If your *entire* design is made with one of these languages then okay. Hook up custom code around that core and you are screwed if things do not work.