Re: Most Surprised
Whether CISC or RISC (a useless distinction nowadays, how about simpy "ISC"), there needs to be instruction pipelines. Otherwise how are you going to keep the various elements of the chip busy. Indeed, pipelines were just on RISCs in the first place to be able to issue an instruction at every clock cycle: RISC pipeline.
OTOH, this pipeline seems very deep. Recovering from a bad branch (i.e. emptying the pipeline, then refilling it) will take a few cycles.
Well, it would probably take a few hours to study the design in detail. Not my area now..
It does mean that this is useless for hard real-time applications. Branch execution time is now impossible to predict.
Well, "hard real-time" is still in the ms range, right, a few orders of magnitude slower? I don't think this is going to matter.