You are correct - as die size increases the chances of a die being affected by an imperfection. Die sizes have increased by about 20% per additional 2-cores (ignoring hyperthreading):
4 core: 124mm2
6 core: 149mm2
8 core: 174mm2
My estimate for utilisation decreases via larger die sizes was 33% to include the die size increase, imperfections and lower number of dies per wafer.
The 50% figure for the comes from using two chiplets on one package (i.e. Cascade Lake AP) - the scaling is exactly 50% because the number of imperfections remains the same within the existing die yield.