Reply to post: Re: "I did not know that ARM actually prohibited adding instructions"

Talk about a calculated RISC: If you think you can do a better job than Arm at designing CPUs, now's your chance

Anonymous Coward
Anonymous Coward

Re: "I did not know that ARM actually prohibited adding instructions"

My understanding is that ARM ISA's have coprocessor instructions:

- COPROCESSOR DATA XFER (LDC/SDC/LDC2/STC2)

- COPROCESSOR DATA OP (CDP/CDP2)

- COPROCESSOR REG XFER (MRC/MCR/MRC2/MCR2/MCRR/MRCC/MCRR2/MRCC2/FMDRR))

These allow you control multiple coprocessors but you don't get to modify the ARM ISA itself. There maybe additional instructions that I haven't included, it's been a few years since I looked into this...

The management of the coprocessors leads to a small amount of overhead that is likely becoming an issue as clock speeds go past 2GHz (likely lower) as the interface CPU and coprocessor have to check availability via a common interface to see if the coprocessor is available to take more instructions. Moving that to the ISA would allow you to avoid or reduce the check and incorporate sufficient resources to handle synchronisation and concurrency without impacting other coprocessors or the CPU.

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