Reply to post:

Hate Verilog? Detest VHDL? You're not the only one. Xilinx rolls out easier-to-use free FPGA programming tools after developer outcry

Aspen Logic

Time to market matters but if you can not debug your design then how quickly you got to gates does not matter one iota. Software development tools permit straight forward debugging techniques. Not so with logic designs, and especially not ones from C/C++ which actually make the problem 10-100 times worse!

POST COMMENT House rules

Not a member of The Register? Create a new account here.

  • Enter your comment

  • Add an icon

Anonymous cowards cannot choose their icon

SUBSCRIBE TO OUR WEEKLY TECH NEWSLETTER

Biting the hand that feeds IT © 1998–2019