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Hate Verilog? Detest VHDL? You're not the only one. Xilinx rolls out easier-to-use free FPGA programming tools after developer outcry

Anonymous Coward
Anonymous Coward

Well - that "obvious" aid for FPGAs has only taken nearly 34 years. I always hand-crafted my Xilinx designs in 1985-88 at gate level. That gave maximum density and control over the interconnect routes for time critical paths. Admittedly - there were only about 1800 gates to play with.

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