Reply to post: Re: well done

Linus Torvalds pulls pin, tosses in grenade: x86 won, forget about Arm in server CPUs, says Linux kernel supremo

StargateSg7

Re: well done

I should note there are over 120 Hardware/Software Engineers working on the OPTIMIZED CPU, GPU, DSP, MCU FPU, and yes even PIC (Programmable Interrupt Controller) which have MAPPED the chip-specific instruction to EACH of my custom Virtual Instructions.

I (and ONLY ME!) did the ENTIRE FRONT-END compiler which outputs the Virtual Instruction Set from C/C++, Pascal, Basic and YES even Fortran Source Code. The engineering teams created HIGHLY SPECIALIZED and COMPLETELY OPTIMIZED chip-specific instructions that MAP-OUT to and MATCH the intent of the virtual instructions. The text editor is standardized Brief-like which many in IDE systems tends to use, so I didn't have to worry about creating the text editing part, I just needed to hook the Brief-like text editor into my middle-ware parser and compiler.

The ONE KEY part of all our code is that EVERY sub-routine uses Try-Exception-based error trapping so at the very lowest of hardware levels, our code will ALWAYS output a proper signed integer error and/or status code and a multi-lingual error and/or status string to a SINGLE standardized token-handling library which is automatically trapped and error-handled in upper layers. This makes our output code almost bullet-proof!

No weird crashes or pop-up windows as we design EVERYTHING to be error-trapped and handled. There is a 3% to 5% speed penalty but we care more about runtime-safety than pure speed. We can always throw more processors and network nodes at a problem if it needs it. In fact, we have tested the compiler out to "Critical Systems" scales which allows it's use for Nuclear Systems, Aerospace Flight Control and Large-Scale Transport and Critical/Medical/Mass Machine Control applications. Multiple ISO and Mil-Spec standards are adhered to for the UTMOST in long-term uptime and CRITICAL SYSTEMS SAFETY where WE DESIGN FOR a "Fail-Gracefully" mindset of ALL HARDWARE-level and upper-level Communications and Application Layers.

This has worked for over 15 years and it now takes the parent company mere weeks to do large-scale development for use on multiple platforms versus BEFORE that 2005 period, where the average project took TWO to FIVE YEARS to complete!

Again, the reasoning BEHIND THIS is creating long-uptime software (i.e. DECADES without a reboot!) that reacts GRACEFULLY to hardware and software failure to such a level that we can, if necessary FAIL-TO-SAFE-STOP and/or MITIGATE-AND-CONTINUE-AT-SAFER-LEVELS for EVERY part of our code library. Our code is so safe we can drive a car/truck at beyond Level-5 AND fly a space shuttle SAFELY AND FULLY AUTONOMOUSLY !!!

AND because we compartmentalize everything, we can actually MATHEMATICALLY PROVE and RESTRICT sub-routine inputs and outputs to specific acceptable values and ranges on an automated basis for all the lawyers and safety engineers who would like to do their due diligence on our systems.

So again, ONE PERSON did the front-end compiler, but MANY PERSONS did the optimized and HIGHLY ERROR-CHECKED chip specific code! The parent company has technology many people would find utterly STUNNING! How many companies can create 128-bit Gallium Arsenide Substrate combined-CPU/GPU/DSP superchips that run at 60 GHz up to TWO TERAHERTZ? I would say a very very FEW...less than ten worldwide organizations I would say can do that!

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