Re: "can the fault detection system work fast enough. "
"or a discrete ECL SSI logic chip design at 1GHz (it'll guzzle electricity during the minutes of launch with the escape system is usable, then shut down)"
If it doesn't need to be rad hard that might be overkill. But yes, I once did an outline design for an ECL subsystem (bitslice) which would have run at about 200MHz, back in the days when 4MHz was a fast CPU. It needed to run for about 20 seconds max, after which it was redundant because either the incoming thing had been taken out, or you were dead and didn't care. And it was intended to run on dry batteries.