Reply to post: Re: Observations

Roughly 30 years after its birth at UK's Acorn Computers, RISC OS 5 is going open source

MOV r0,r0

Re: Observations

Well it's not like they had a choice - they couldn't do the former as there was no 6502 replacement that suited them so they did the latter. I think the article implies that.

This was an age when eg IDE was a novelty, the problem was that Acorn were used to doing peripheral control on the CPU to cut hardware costs and arrive at a viable price point but you can't have your CPU disappearing into it's own microcode for a dozen (plus some random number of) clock cycles without your OS thinking the hardware has failed. IIRC MUL was the first ARM instruction to take more than one clock tick and if you watch an ARM running RISC OS it's forever jumping into and out of Supervisor Mode.

There's no need to be revisionist over the history. The truth is the Master series hung around in education for an embarrassing length of time and left the door open for the competition which consequently sealed Acorn's fate. That ARM didn't disappear is 50% excellent judgement and 50% good timing/luck.

As for unhackable, as with BBC MOS, RISC OS routines were called through vectors plus those OS ROM modules were fully relocatable and could be replaced by soft loaded RAM resident versions and often were cos patching. Hacking the OS was half the fun and yes, still got mine too.

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