Reply to post: The old block layers problem

Intel boss admits chips in short supply, lobs cash into the quagmire


The old block layers problem

"36nm metal pitches with self-aligned quadruple patterning and multiple block layers is probably the problem."

I hadn't, myself, yet identified this as being the particular problem, but I'm sure I would have got there in the end ... Maybe around the time Intel got round to implementing a 3pm plasma pitch with ai-aligned nontuple tessalating and dancing block layers system.

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