Itanic was wildly successful ...
The announcement alone ended development of architectures it was supposed to compete with. When the first implementation was ready for evaluation it achieved its second main goal: it needed so many transistors that no-one else could build a compatible product. It could sensibly compete on power usage with a toaster despite getting worse bench mark score than cheaper cooler CPUs available at the time. After years of delays, when a product did reach the market, the final main goal was achieved (after a fashion): the price was at the high end of a monopoly product. The only problem was (large NRE)/(small sales) made the cost about equal to the price.
Having the compiler make all the decisions about instruction ordering in advance sounds really cool until you remember some real world problems: do you order the instructions based on the time required to fetch data from the cache or from DRAM? Guess wrong and data is not in the right place at the right time. All the scheduling decisions made by the compiler become garbage. What if the hardware it optimised to spot multiply/divide by 0 or ±1? Again result arrives ahead of schedule and the CPU has to re-order everything.
I am not surprised it took Microsoft years to come up with something worth committing to silicon. I would expect more years to pass before they get performance/watt close to a modern X86/ARM.