Reply to post: Re: Time for NUMA, Embrace your Inner CSP

Hate to ruin your day, but... Boffins cook up fresh Meltdown, Spectre CPU design flaw exploits

Anonymous Coward
Anonymous Coward

Re: Time for NUMA, Embrace your Inner CSP

Thanks for the CSP references, best of luck with them too, though the marketdroids and 'security researchers' won't thank you for them. Maybe there's a DevoPS angle on them somewhere?

A full version of the CSP book appears to have been legitimately freely downloadable for the last few years, see e.g.

One thing I've not seen quite so explicitly mentioned (though your NUMA references come close) is the role of the memory consistency model, and to a lesser extent, what a process (nb process not processor) can and cannot be permitted to see, directly or indirectly.

As far as I know, modern RISC processors have tended to be built around a memory model which does not require external memory to appear consistent across all processes at all times. So if some code wants to know that its view of memory is consistent with what every other process/processor sees, it has to take explicit action to make it happen. Especially where the processor is using complex multilevel cache to provide interesting performance. Hence things like conditional load/store sequences found on ARMs and Alphas and... As it happens, they're the kind of thing that NUMA people have been thinking about for years, and CSP people before them. It's a solvable problem, and non-Intel people had solved it.

As far as I can see, x86 (even modern ones) dates back to an era where there was only one processor and memory consistency was something that software designers or even system designers could happily ignore, because all memory was always consistent. Except it wasn't really.

ARM and AMD64 do not seem to assume this legacy behaviour and as such they miss out on some of the recent fun.

I could be wrong though. Where can readers find out more about this particular historical topic and its current relevance?

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