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AMD sued: Number of Bulldozer cores in its chips is a lie, allegedly

Marcelo Rodrigues

"It seems to me that the plaintiffs are using the term 'instruction[s]' in a very specific, restricted sense to mean a "complex math calculation" and therefore one that must engage the shared FPU. Unless I am gravely mistaken, however, there are plenty of instructions that would not need to engage the FPU."

Yes, but it is worse than that.

The Athlon FX FPU is a 256 bits part. It can process ONE 256 bit operation each time. BUT it can process TWO 128 bit operations simultaneously - or even four 64 bit operations!

So, it is a little more complicated than "on FPU equals to one processor" argument. Would he be happier if each core used a 128 bit FPU?

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