You're correct, but the important thing to note is that as chip dimensions shrink the hot spots become more and more concentrated, and because silicon's thermal conductivity is less than a tenth of this material, it doesn't spread laterally through the chip very well.
By having a high conductivity material affixed to the silicon die, the heat will be drawn out of the silicon and into the graphene film - where it can then be drawn out of the graphene by your existing heatsink. The heatsink would have a lower thermal conductivity than the graphene film but its mass will be far greater than the chip+graphene and thus be able to soak up a lot of heat while still maintaining an acceptable thermal gradient for good performance (which can be helped via fans, heat pipes, etc.)
I wonder if it would be possible to put the graphene layer in between stacked chips, as heat removal from stacked dies is one of the limiting factors of the current state of the art.
Biting the hand that feeds IT
