IBM debuts new Power7 iron this week

@Matt

WTF are you talking about!

Any AIX code that is compiled with the compiler defaults will work. It just does, and has done for years.

There is a good chance (greater than 80%) that if you pulled a binary compiled for RS64 or Power2, or even the original RIOS chipsets from a system running AIX 4.3.2 or later, and placed it *WITHOUT CHANGE* on an AIX 6.1 system running Power7, it would run.

*IF* you are talking about extracting every ounce of performance for some code, then I agree that if you have optimized the code for cach size and processor affinity or the particular properties of the floating point pipeline (as is being done where I work currently) or any number of other factors, you will need to re-compile it with the relevant options to get the best performance, but even then the Power6 optimized code will probably run on Power7. This is not new nor specific to IBM processors, and hasn't been ever since I was working on PDP/11's and VAXes.

It is acknowledged that there will be a different execution profiles for Power7 from Power6. The design requirements for the processor were different, and I talk to some worried people talking about how scalable their model is at the moment. We currently have some code that tops out at about 768 processors, and gets worse if you increase the number above this. If the overall clock speed is dropped without a corresponding increase in the number of instructions per clock cycle, then this code may well be slower on Power7 than Power6.

But it's not certain. The speed of the level 3 cache, together with the less deep pipeline required for slower clock speeds may just offset the drop in overall clock speed (pipeline stalls become less of a problem). And as the bottleneck with the code is in inter-thread communication, the high bandwidth between cores on the same die, and on the same QCM may also offer realistic hope of performance gain. And the interconnect between the nodes in an IH supernode should also perform better than what is currently used. And I believe that the number of possible in-flight speculative execution threads possible with more available execution units may reduce pipeline stalls even more.

Remember the Pentium 4 vs. Pentium 3 debacle, where a Pentium 3 at the same clock speed out performed the Pentium 4 when it was first launched, and the follow up Pentium M and D processors dropped the clock speed and again outperformed a Pentium 4.

The talk of in-order vs. out-of-order is bogus. The results for the same stream of instructions should be the same regardless of whether it is in-order or out-of-order. If it's not, the processor is broken. The difference is that out-of-order may allow the hardware instruction scheduler to better utilize the available execution units, leading to more-instructions per clock.

And anyway, the only applications that really are affected by the clock speed are speed-daemon floating point hungry single threaded research types of workloads. From my 30+ years of experience, this is a very small (but admittedly valuable) part of the AIX customer base.

For your commercial workload customer, the difference between Power5, Power6 and Power7 architecture and instruction sets will be largely ignorable. What will be more important is the number of cores, the number of simultaneous threads that can be executed and the memory constraints of the hardware. For these customers, the application providers may not even have optimized versions of their code for the different processors, but a one-size-fits-all distribution. Power7 is probably a big step forward for them. I know application providers who still compile on Power4 hardware with a generic set of compiler switches to allow the code to run on the entire processor set.

In fact, AIX is like this. The version of AIX 5.3 that runs on the Power6 575's (the current speed freak machine) is EXACTLY THE SAME as that which runs on an RS64 44P 170 (same install disks, I know, because I have done it!). There is no distinction on FixCentral for patches. It is just all the same.

Your comments about AIX5.3 are interesting. Yes, there are some features that will not be available to AIX5.3. Things like Turbo mode. But AIX 5.3 is still supported (not sure if there is an end-of-life date yet, would expect it if and when AIX 6.2 or AIX 7.1 is available), and there is likely to be a new Technology Level (TL12?) for Power7 that will add some of the new features. IBM have always kept the latest 2 releases of AIX under active support, and normally publish withdrawal from marketing for an OS about 2 years prior to that date. This means that there is at least 2 years of AIX 5.3 support, not that I would recommend anybody installing Power7 to use AIX 5.3 at this time.

The instruction features are more likely to be conditioned by the compilers (which, incidentally, are currently OS version agnostic, the Fortran and C compilers are the same packages for AIX 5.3 and AIX 6.1). What's even more impressive is that you can compile Power6 code on, say, a Power5 system, drop it onto a Power6 box, and expect it to run as well as if it had been compiled on a Power6 system.

All of this does not sound like the scenario you paint. Maybe you ought to work in a big AIX shop sometime, and see what binary compatibility is really like.

BTW. I cannot say where I am working, but we have more than one cluster in the first 100 of the November 2009 Top 500 Supercomputer list.

Get a grip Matt (if this really is Matt talking here)

Matt, you are to intelligent for this broadside. Let's try to debunk this well.. lack of knowledge. I always like to see the best in people.

InOrder versus OOO.

Is POWER6 an inorder core. Yes. It sure is. Do I think it was totally bonkers to make a inorder (Mostly Inorder as FP instructions could actually be .. well now it gets tricky, cause there is both an issue and a shedule on POWER.) out of order, I sure did.

Will this have an effect on code compiled for specific for POWER6. Yes. How big is this ? I don't know.. I just know that I was involved in a tuning project last year, where we moved the same binaries, and mksysb and all from POWER4->POWER5->POWER6 and our performance numbers hit exactly what we expected +/- a few percent on rPerf. So.. well.. Also as several people have mentioned here then you get new versions of the critical libraries with new patches. But if I were to handcode a piece of code, link it statically for POWER6 and on POWER6 and then run it on POWER7 would I then get a performance hit you can see. Sure..

"P7 is a return to little more than lots of P5 cores shrunk onto the same die"

That is just wrong and you know it. POWER7 is a whole different beast as you can see here:

http://eecatalog.com/power/2009/10/09/power7-power-pc-processor-cores-2/

The differences are so many, that this link should be enough for even the hardest sceptic.

IMHO the reason why POWER6 is different is cause it was originally intended to slot in the mainframes also.

This is of cause just pure speculation on my side, but perhaps someone here knows better than me.

"Which means any apps written for P5 had to have a rewrite to run best on P6 (otherwise they could even perform WORSE on P6 than they did on P5!), and now P6/6+ apps will need a rewrite to be optimised for P7. He also knows that the few new features in P7 won't be unlocked until customers get the next gen of AIX, version 7.x (by the way, when is that likely to be?). All the P6 apps won't work to their best until they're rewritten for P7 and AIX 7.x (and all the iSeries apps too will need updating by the look of this article). And considering that only a fool would put a brand-new version of an OS into production, that means at least six months (probably a year) after the Power7 servers actually become available to customers they will still be stumbling along with AIX 6.1. Who knows when the combination of new CPU, new chipsets, new OS and rewritten apps will be ready for primetime? 2011?"

What the f word are you talking about ? Rewrite the applications? Why would you need to rewrite the applications to take advantage of a new generations of processors ? It makes absolutely no sense. And you talk about chipset and new OS. Basically

dy knows that you won't get the same performance out of POWER7 on AIX 5.3, it doesn't support SMT-4.

nce report that describes the rPerf numbers you will get on AIX 5.2.

ftp://public.dhe.ibm.com/common/ssi/pm/rg/n/poo03017usen/POO03017USEN.PDF

For example you only get 73.81 rPerf on a 16 way 2.2Ghz POWER5+ p570 machine on AIX 5.2 compared to 95.96 on AIX 5.3.

IT IS NOT A SECRET.

And you don't know much about how iSeries work.

// Jesper