Japanese CE firms partner on 'standard' CPU project Seven Japanese consumer electronics companies and chip makers are to launch their own CPU. The unnamed part is still a few years away: according to reports, it'll be out by the end of the partners' 2012 financial - not the same thing as calendar 2012, so probably April 2013 at the earliest. Co-funded by the Japanese …
OK, it didn't exactly take me long to find this. How is it that there are scores of vacuous sound bite articles out there (including el Reg) that simply spout the same drivel, and never bothered to find out what is going on.
So, listen up. This is interesting stuff.
One, it isn't a new ISA. So worrying about whether it competes with x86, Arm, or anything else is not even asking the right question. There was a prototype of some of the ideas involved that used x86 chips (or Power). Some of the ideas, not all.
There are two key ideas.
First is a new set of language additions to help specify parallelism so that the compiler can create good parallel code. This competes with things like OpenMP. At a cursory look over the language additions they look good. There is an extant compiler that works, and they have tested and measured real workloads, and it looks credible. Of course this would work on any modern multiprocessor, and is intended to. The API (called OSCAR) is defined on C90 C99 and Fortran90. There is a clue here about the intended use of the system.
Secondly, and something that answers the question - "what does an API have to do with power use?", is that the design provides for clock and voltage control, under the control of the API. Which is certainly new. The idea being that if the compiler has scheduled the parallel code, it knows exactly what cores need to run, and even which cores may finish a task earlier, and thus can be throttled back to save power without changing the time to complete the overall task (since power scales as the square of the speed this wins over just powering down when it finishes, which is linear) Clearly this is the point of the alliance. No new ISAs, but new multi-core chip systems, using existing CPU ISAs from the partners - mostly targeted at embedded consumer electronics, all systems implementing the power control functions demanded by the OSCAR API.
They show an example where an 8 core system with this power control enabled sees a 74% reduction on power over not using, it for an MPEG2 video decoding task. This is pretty impressive. The 8 core system is a one chip system done in concert with Hitachi, and no doubt using one of Hitachi's existing CPU cores as its base.
There are some pretty demo systems, one powered by a solar panel, so maybe this is where some of the odd reporting is coming from.
For some reason, CE manufacturers are poor at good IDEs and software development in general. Look at VxWorks - my experience was that it was dire compared to any PC based IDE... not sure what Windows CE is like except that the ticket machine in my local station often has a Windows CE screen of death up...
" As far as we can tell, the part won't use the x8 instruction set, so claims that the chip is intended to mount a challenge to chip giant Intel seem wide of the mark".
That is a funny sentence, indeed.
To beat Intel you have to scrap any x8 in the first place as it is definitely a dead end (long ago) as an "invention", to build on.
Intel lost the memory business to Japan some 20 years ago, due to falling asleep
And in the processor business they are soundly asleep with the X8 (no matter how many cores.)
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