Here's a bit of Intel for you: Neri a day goes by that HPE doesn't feel CPU shortage pinch Hewlett Packard Enterprise is feeling the effects of Intel shortages in the server market, the company CEO has told us. An industry-wide CPU shortfall has dented sales of PCs and servers since last summer as Chipzilla struggles to switch to a 10nm manufacturing process, with chip production focused on higher-margin server- …
I saw this on Reddit, so the idea is not mine. But the Intel shortage has nothing to do with 10 nm. That is a lie Intel is promulgating. Prior to Ryzen, Intel was quite content on selling us 4 core chips for a large sum, 6 core for a really really large amount. But here comes Ryzen with an 8 core chip at the same price as their 4 core. Suddenly, Intel has to increase the cores. What was once an i7 is now an i3. And that mega-expensive 6 core i7, well now that is an i5. More cores means a bigger chip. Wafer space is still the same. So Intel is now having less CPU's coming off a wafer because they are bigger than they were before AMD made mega-cores cheap. Less CPU's produced means less available. Thus a shortage.
"But the Intel shortage has nothing to do with 10 nm. That is a lie Intel is promulgating."
Simple math:
- in 2018, Intel had 4 active 14nm fabs and 2 unused 10nm fabs
- in 2019, Intel has 5 (a 6th fab is coming online or may already be producing) active 14nm fabs and 2 (3 in 2020) underutilised 10nm fabs
As you mention, core counts are increasing resulting in a decrease in die's per wafer (~33% less production capacity) and in some cases Intel is doubling up existing die's in the finished product (i.e. effectively a loss of 50% production capacity).
If you put arbitrary numbers per fab, once Intel have all 6 14nm fabs up and running they will only match their capacity at the beginning of 2018 before the latest core count war started.
Having 2+ idle 10nms fabs is the primary issue as it results in a 33% capacity decrease. While I acknowledge not having newer designs (i.e. more IO/memory bandwidth) to allow them to compete with AMD or a chiplet type design for larger dies doesn't help either, they are single figure percentages.
If you double the die size, the number of chips per wafer will be less than 50% of what it was before.
Imperfections per wafer will be much the same as before, and will likely affect about the same number of chips per wafer as before, but that would be a higher proportion of the total.
To give an extreme example, if yield per wafer was previously 50%, if you double the chip size, then the yield could fall to almost 0%.
You are correct - as die size increases the chances of a die being affected by an imperfection. Die sizes have increased by about 20% per additional 2-cores (ignoring hyperthreading):
4 core: 124mm2
6 core: 149mm2
8 core: 174mm2
My estimate for utilisation decreases via larger die sizes was 33% to include the die size increase, imperfections and lower number of dies per wafer.
The 50% figure for the comes from using two chiplets on one package (i.e. Cascade Lake AP) - the scaling is exactly 50% because the number of imperfections remains the same within the existing die yield.
Pry the heatsink off the top, and you'll see chiplets with a load of CPU cores on them, clustered around a central IO chiplet.
One benefit to AMD is that if say one core core on a quad chiplet fails, and they don't sell a 3 core CPU, they don't have to bin it. They can pair it with another 3/4 success and flog it as a 6-core.
The larger die sizes also significantly increases chances of die failing because of a flaw which also reduces output.
AMD has the advantage of chiplets which means less rejects
(Chiplets also mean more flexible production as AMD can order higher volumes safe in knowledge they can stick the chiplet into whichever CPU is most popular a few weeks down the line)
There are two areas where increased die size affects number of dies per wafer:
- defects
- positioning
The impact of defects is difficult to know unless the manufacturer releases the details as redundancy or disabling defective areas affects what you can use. On top of this, the ability of the design you are using to be successfully etched will then give you your final yield.
From what I can tell, on the AMD side, the Zen2 CCX should yield between 750+ dies per wafer based on its size - I've ignored the IO die as it shouldn't affect the number of usable parts significantly. Yields are reportedly in the 68%-73% range.
On the Intel side, the 4-core Coffee Lake is around 415/wafer and the 8 core part is around 275/wafer. Yields are reportedly around 75%-80%. Intel benefit from a more mature process with yields.
I've assumed 300mm wafers for all parts.
It is also all the 14nm modem chips they are supplying to Apple - over 200 million a year now that they are used across the whole line including older iPhones they still sell.
Back when they inked their agreements with Apple I'm sure they assumed they'd be on 10nm long before this became an issue. When they remained stuck on 14nm, supplying 200 million chips to someone else (and Apple's contract not allowing them to say "sorry, there's a shortage, you'll have to take less than you need") was a major reason for the shortage.
Just look at the times when Intel said there was a shortage - right when Apple went to 100% Intel modem chips instead of an Intel/Qualcomm split. Look at the times when Intel said the shortage was easing up - in early part of a year, when Apple's seasonal sales fall off and they need fewer modem chips. Then when summer hits the shortage does again because they are ramping modem chip production for a new iPhone launch. It has been like clockwork, and exactly matches Apple's demand.
'HP Inc, Lenovo, Dell and a raft of others have all bemoaned Intel's protracted production problems.'
Moaning to Intel via press releases is all well and good but if you are still buying as much as they can sell you maybe a change of tactics is required?
I know someone that has a great new product and will probably bend over backwards to get more market share, all you have to do is stick them in decent configuration and most of your customers would never know the difference!
"yields of 5nm for AMD are already over 7nm"
Any reference? TSMC is struggling with yields for 7nm+ due to the relatively few additional EUV steps.
5nm has a significant number of EUV steps and the equipment to do it is only just being installed (in theory - it may need another generation) and EUV will depend on yields AND processing speed as EUV results in a significant drop in wafers per hour due to power requirements for etching resulting in downtime and alignment challenges..
Hmmm....
"TSMC's 5nm process has crossed 50% yield according to the report (which is what the yield for 7nm supposedly is right now) [edit: seems to be a translation error] "
Yields have been >65% for AMD since moving to 7nm and low power designs were reportedly yielding around 80% so this sounds incorrect.
The following article suggests TSMC is actually 50% through their test cycle for 5nm - https://adoredtv.com/is-5nm-actually-at-50-yields/
My guesstimate is that puts them around 6 months away from being production ready. That should mean low power is available for test runs mid-2020 and production in Q4. High performance testing is likely to begin when low power is in production which puts production around Q1/Q2 2021. i.e. 5nm is on track.
The question for 5nm will be volume - EUV is significantly slower per etching unit than DUV (ASML quote EUV is 125 wafers/hour vs DUV at 275 wafers/hour and EUV isn't able to run continuously at present due to maintenance requirements for EUV source).
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