The Lance Arm-strong of performance-enhanced CPUs: Armv8.1-M arch jams vector math into super-microcontrollers Processor designer Arm will, we're told, today pull the wraps off its Armv8.1-M architecture for crafting next-gen 32-bit microcontrollers. This technology is expected to be the foundation of future beefy Arm Cortex-M CPU cores that chipmakers can license and stick in their components. For buyers of stuff, like you and me, …
I think the most memory I've seen paired with one of these is 512k, and 32k is quite typical. Of course, they probably have SOCs with more memory somewhere if they're planning to do voice recognition on them, but that gives you a sense of the typical scale of the things. They run one program, connected to a few basic hardware devices, and nothing else.
It's interesting that this, MVE, is even necessary.
ARM's previous vector instruction set, SVE (for Scalable Vector Extensions), was announced in August 2016 and I believe is not yet shipping in any of ARM Ltd's cores yet, but only a Fujitsu ARM-based supercomputer processor).
And yet here we are with yet another vector processing instruction set announced.
Perhaps SVE didn't prove to be so scalable?
Meanwhile, the RISC-V Foundation's "Vector Extension Working Group" has been (frustratingly) slowly hammering out differences between microcontroller people and supercomputer people (and everyone in between) and since since earlier this month have a draft spec that probably several member companies will have available in silicon this year.
It looks as if the RISC-V V spec (with stable draft completed before anyone heard about MVE) scales to cover the whole ground covered by both MVE and SVE, as well as legacy SIMD ISAs such as NEON, AVX, SSE, MMX, while being very easy to use.
It's very interesting that in the MVE documents ARM talks about concepts such as executing vector instructions in beats, and chaining successive vector instructions together, because the RISC-V V spec is built with exactly the same (Cray-inspired) concepts in mind, as was the earlier "Hwacha" vector processor work at Berkeley six or eight years ago that RISC-V originally emerged out of.
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