Any such plan needs to start by recognizing certain painful truths.
"Exascale computing" is a data centre task
And in the data centre the x86 architecture rules.
Yes it's a fu**ing dinosaur of a code museum which Intel have bolted stuff on over the years to make it look like a real processor architecture.
Consider they tried to clean sheet the problem with Itanium and look where that went.
So you need to start by developing the tools to reverse engineer any ISA and reproduce it with a hard wired design. A modern x86 variant has probably close to a 1000 different instructions.
Eliminating microcode is about the only way you'll get a processor which runs faster than Intel on foundry processes. IOW 6502, not Z80. People will point to ARM but the instruction set for ARM was designed to be easy to map into the control signals to internal PLA's, with few instruction formats. It's the smart way to go, if you have a clean sheet to work with.
Compare that to the multiple, baroque instruction formats of the Intel Pentium whatever of today. You're virtually looking at a context free grammar to decide what one to use right there.
So developing the tools that can implement such an arbitrary ISA would see Europe well placed to design any future ISA they wanted,
Historically the drill has been IS --> set of input patterns --> PALs or microcode -->outputs. But with much greater processing power why not go back to actual hard wired gates, eliminating the gate delays of driving the long lines in the PLA's or the microcode ROM addressing?
IOW a toolset from Arbitrary ISA and register set --> logic design --> logic optimization --> chip layout.
Of course if you can make the resulting chip pin compatible as well that would be better.
I'd start trying to do a single processor without any cache. I think that'll be tough enough.