Boffin supercharges FPGAs with timing signal tweak A Swedish researcher has discovered a new way to optimise FPGA performance, with as much as a five-fold boost on offer. However, it's been a long and painful process for researcher Carl Ingemarsson to get to publication, including having his work plagiarised three years ago. The problem for then-undergrad Ingemarsson, of from …
That someone else seemed to include on of the co-authors of the (later, unplagiarized) Carl Ingemarsson paper. So was it a colleague trying to get two-for-one papers out of it? How did he get to stay on the joint paper if he participated in that plagiarization?
The IEEE's withdrawal note states that only the first and last authors (Imran Ali Qureshi and Ghulam Muhammad Shaikh) are culpable in the plagiarism. The middle one, Fahad Qureshi, is apparently not to blame.
Its entirely possible that he was added as a co-author to give the paper a greater appearance of legitimacy and never actually read it. (Against the rules: he probably signed something to say he had).
Its also possible that Fahad Qureshi was bought onto the Swedish paper after it had mostly been written, to reflect some genuinely useful contribution that was in the Pakistani paper, which was not enough to give it legs by itself but which was worth bundling with the Swedish work.
Whatever the sequence of events its hard to image that there is much love between the Swedish group and the Pakistani group right now.
Smiley face for the poor SOB who worked on this for years while others tried to snatch the credit.
Doing it on an FPGA might or might not have be ingenious, but the concept is far from new. Back in the late 60's and early 70's you achieved the same clock skew effect on mainframes such as those made by CDC by adjusting the length of the connecting wires on the backplane. The greater propagation delay of a longer wire ensures that the data arrives at the pins before the clock signal that processes them. Many field change bug fixes were implemented by swapping out wires for longer or shorter ones. Clock speeds were of course rather slower in those days.
Kind of off topic, but amazing still...
A novel way to do this I saw, used for camcorders etc, was an acoustic delay.
Small piezoelectrics setup to receive an ultrasonic pulse, which is beamshaped around a course so as to give an exact delay. Multiples in one little panel, and you can setup things like display scanning and timing.
Ultrasonic Delay Lines: https://youtu.be/tQyX3F4ggM8
Or if you go back further, mercury-filled ultrasonic delay lines were uses as computer memory in the 1940s/1950s -- except they were six feet long, with a hundred of them fitted into a rigid anti-vibration steel frame weighing several tons (holding five tons of mercury!) , and had to be kept within a degree of the design temperature...
http://mraths.org.uk/?page_id=582
Now *that's* an engineering challenge...
[my father-in-law was responsible for building it, after doing the same on Colossus...]
"A novel way to do this I saw, used for camcorders etc, was an acoustic delay."
IIRC Early networked video terminal displays in the 1970s had acoustic delay lines as a frame data store.
It was said that if you gave the case a hard bang then all the letters fell to the bottom of the screen :-P
Most PhD papers are meh. Meaning that they aren't as radical or disruptive.
This is really cool work and it shows that the tools you get from the OEM isn't always optimized.
This should make those working for the vendors stand up and say 'doh!' .
Again Thumbs up for a good job.
Named, shamed and caned!
My partner recently had this, she presenting at an FDA led conference in the US. The presenters are required to submit slides and attend conference calls before hand, on the 2nd call she discovered one the other presenters had completely rewritten their presentation to mirror hers, basically stealing her idea and half her slides.
Wouldn't have been so bad, but the person is question had also wangled to present their slides before my partner (and hence getting the recognition).
There really are some despicable people in this world :(
> ...(and hence getting the recognition).
Argh! I'd immediately complain with whoever holds that conference. Copyright could be another venue, she should be able to prove that (some of) the slides originated from her.
What I wish to plagiarizers. ------------>
It seems to work as
Map algorithm to --> generic FPGA architecture
Re map algorithm --> specifics of FPGA architecture.
I guess the problem getting it published would be "Why don't the FPGA mfgs do this already in their SW?"
The honest answer is probably "Because they want to sell chips. As long as the design algorithms good enough, and fast enough for their products they don't really care about optimal routing, and of course everyone knows if you really need the last iota of speed you go to ASICs anyway."
Turning the conceptual logical building blocks of the algorithm into the HW building blocks on the chips is often called "compilation." It seems FPGA vendors will re-discover the "optimize" stage, where the system takes more time to generate a more efficient result. This will no doubt be announced as a massive leap forward.
As for changing cable lengths in a mainframe. This was mentioned in ref to Multics, but because the GE645 didn't have a central clock, it was all asynchronous. Lots of "timing" signals but not a central "clock" signal as such. Something did something once a pulse got to it down a piece of specif length coax. Needs more time? Stick in a longer cable. Speeding up would have been more difficult, as you'd probably need to shorten multiple cables to get the result.
What I can't get about FPGA is individual transistor toggle speeds have continued to climb over the yeas. They've got to be over 10GHz by now.
So WTF can't you get an FPGA that can routinely map algorithms that run at > 1GHz?
If it's because they are all using the same poor mapping algorithms we might be in for quite a performance boost in the next few years.
This seems to me to be a consequence of modern design practice. As things get bigger (RAM, processor speed, bandwidth), there's a decreasing need to optimise and thus no pressure to develop an understanding of the architecture.
I used to design FPGAs back when they were small and expensive, and spent lots of time tweaking designs to get them to fit at all. This often meant moving logic around the chip as there were not enough interconnections between the sub blocks.
Nowadays, they're all programmed via VHDL with each manufacturer's compilation tool doing voodoo magic to program the chip. It's not surprising that performance is sacrificed.
FPGA tools do seem to throw the logic blocks up in the air, see where they land, then shuffle them around until they fit. Saving engineers the time of doing that themselves, at the cost of being potentially less optimal than it could be.
That this could adversely impact clock rates and throughput is something which I believe has long been recognised. Putting emphasis or priority on routing clocks when placing and shuffling things around seems to be the obvious answer.
So I can understand why Ingemarsson's research which proved the point and the argument for doing so wasn't considered that novel nor revealing. Some would say all he really did was restate the already known; that a better algorithm, more suited to achieving a particular outcome, will better achieve that particular outcome.
There was a problem with using the Xilinx FPGAs in the late 1980s. A small change to the logic using the standard design tools often changed the existing timing signal routing elsewhere. This wasn't using high level VHDL.
We had a design that was jam-packed on a 50MHz part - with a critical clock constraint. I devised a method where we could add a change without unexpectedly affecting the existing proven routing of the rest of the FPGA's logic.
We never published anything as the overall design gave us a very good selling margin compared to our competitors. The standard "brute force" technology they used established a higher market pricing for the final class of product.
We saw no reason to try to undercut them and signal our innovation for them to reverse engineer. Our product was part of an integrated portfolio. The Company Patent Officer said our FPGA design's only protection would be as a "software" copyright - and would not be considered patentable.
Its quite fun to try and reconstruct what happened here.
The apparently non-culpable author, Fahad Kureshi, did a thesis on FFT optimisation in the Swedish group supervised by the same prof (Gustavsson). In his thesis he lists 10+ publications with Gustavsson on FFT optimisation, including hardware-level tweaks. Therefore he is no amateur and has the full confidence and respect of the Swedish group.
In the thanks list, he acknowledges "My friends and colleagues in Pakistan for their help and care..." and then goes further to mention: My friends... ___Imran Qureshi___ ..... for their kind help in proof reading my thesis.
So the first author of the plagiarising paper (unless its another Imran Qureshi, there are a lot of Kureshis/Qureshis about)..... proofread the thesis of a guy from the group delivering the original work. He didn't do a good job, its still has quite a few spelling and grammar mistakes.
Lets make assumptions:
(1) Imran (Q/K)ureshi asks Fahad Kureshi is he can lift an unpublished chunk of the thesis that he's written, saying yes I'll credit you for the work you've done.
(2) Imran's paper still doesn't have enough meat so he just follows the threads that he already has from Fahad's work and ends up with a duplicate of what Ingmarrson ended up doing under Gustavsson's supervision.
(3) Imran goes to his supervisor, Dr Gulam Shaikh, who is busy with teaching, underpaid and very stressed from the difficulties of life in Karachi. Ingmarrson's paper isn't out, so they publish, claiming to have a legit collaboration with Gustavsson's group, although not actually Gustavsson, which is unthinkable to the hierarchically-minded aryans over in Linkoping.
(4) Gustavsson points out that priority comes from first submission to a journal, not first publication. Despite (maybe) only having been somewhat cheeky, the Pakistani group are obliged to back down. Their mistakes were (1) Treading on Gustavsson's toes by working in a field he was busy in. (2) Using information from his (former?) grad student to steal a lead.
Fahad Kureshi will get a telling off for leaking, but most likely be forgiven.
Imran Kureshi and his boss are going to come in for a lot of hate, I would be interested if either of them reads this post if they could tell me how well I reconstructed this...
Sure you can optimize the design to squeeze out every last bit of available performance, but most of the time it is the sheer size and complexity of designs that is the limiting factor. With FPGA's you have to build the design in a way that you know will work given the limitations of not only the chip architecture but the RTL synthesis and place-and-route tools.
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