back to article Peering closer at 3D XPoint memory: What are Intel, Micron up to?

Asking what we know about Intel/Micron's XPoint memory announced yesterday is maybe the wrong question. What don't we know about it? Here are a few mysteries: Is the technology patented? Have developers kept quiet for 10 years? What is the memory cell material? What is their selector material? What is the process used to …

  1. Jim O'Reilly
    Holmes

    And NO software changes

    I've worked extensively with NVRAM architectures. Any of the byte-addressable tape open Pandora's box on software changes (all for the better, I might add).

    Just using it as RAMDisk doesn't cut it. The OS virtual file system and SCSI stack are too clunky to even try, and they don't provide granularity or atomicity. Moreover, apps need to understand the NV nature of NVRAM memory to take advantage of it. That means compiler and link editor changes galore.

    Then there's the issue of data integrity and a minimum of RAID.

    There's a lot more, but you get the point!

    1. Anonymous Coward
      Anonymous Coward

      Re: And NO software changes

      CPU vendors don't seem to have a problem adding more pins to their products!

    2. Bronek Kozicki

      Re: And NO software changes

      This is no NVRAM, you cannot simply use as RAM any technology which has any endurance limit. No matter if its 1000x larger than NAND. This is "merely" another tier in write cache of your regular data storage, or at best (and I'm thinking that's a niche product - see ZeusRAM) actual data storage.

  2. P0l0nium

    Big question here is:

    - What cards do Samsung and the DRAM players hold ??

    - When will they show those cards ??

    OMG that's 2 questions ....

    1. Mellon

      My guess is that this is rebranded PCM. The other DRAM manufacturers have held back on introducing it because of yield issues and the fact that it will cannibalize DRAM sales (hence the initial introductions as NOR replacements). Their response will likely depend on how Intel/Micron position the products. The hyperscale guys have been asking for cheaper/slower DRAM for quite a while.

  3. Anonymous Coward
    Anonymous Coward

    Micron/Intel

    This. So much for getting much love from techies on that Windows 10 release today. What's in that box? Hmmm?

  4. phil dude
    Thumb Up

    archives...

    would it be possible to use them as archive media? If sufficiently dense, strong mathematics and multiple redundancy might yield an interesting long term memory.

    I am of course thinking of the lack of magnetic or electron reservoir in this regard....

    P.

  5. Anonymous Coward
    Anonymous Coward

    layer limit

    Why will V-NAND stop at 16-64 stacks/layers?

    1. Richard 12 Silver badge

      Re: layer limit

      Cost.

      Every layer adds cost to manufacture, and is another set of failure points that can ruin the chip, reducing yield.

      At some point the cost gets so high and the yield so low that it's not worthwhile.

      1. Bronek Kozicki

        Re: layer limit

        Good point, however: experience so far points that evolution of fabrication processes is very focused on increased yields. Which makes sense, since this is where economy of silicon fabrication comes from. There is no reason to think this should be any different for either of V-NAND or 3D XPoint. Thus I would expect stacking (of both) to slowly increase, perhaps in 2 or 3 years cycle, until some other limit is hit (e.g. current needed to support more layers).

  6. Conundrum1885

    Re. Re. layer limit

    I did hear that 200GB microSD have something like 22 ultra thin chips stacked up (!) to get this level of storage with conventional 19nm TLC chips.

    Needless to say the number of failed chips is slightly less of a problem as sample chips are tested on the periphery of each wafer and if the yield is too low at that point they don't bother to thin the wafer and just use it for low density products.

    Also some manufacturers actually use UV laser diffraction to test die in situ as a "good" chip will generate a distinct interference pattern from a chip with weak/bad areas allowing die sorting on the fly. (probably violating NDA here, better not say any more...)

  7. Anonymous Coward
    Anonymous Coward

    Missed one mystery

    Is it bit/word addressable like DRAM or block addressable like NAND?

    1. An0n C0w4rd

      Re: Missed one mystery

      To a degree it probably depends on the controller driving the chips. It looks like it could be more like RAM, but initial implementations may present it as a block device to aid adoption before trying to create new places in the storage stack for it.

    2. Bronek Kozicki

      Re: Missed one mystery

      Yes it is, makes it really good candidate for write cache. You won't be able to run general purpose software directly on this memory though, due to endurance limit (very high, but still). Unless you clasify "firmware" as "general purpose" ;)

  8. Fungus Bob
    Joke

    3D memory my ass...

    Pictures don't lie - that's just Jenga!

  9. Anonymous Coward
    Anonymous Coward

    One technical question that is unanswered is whether it will sustain infinite reads without bit flips being introduced. Otherwise it looks very good. I hope CPU vendors will introduce load and store instructions that don't touch the CPU caches. That would allow very energy efficient random access lookups in massive hash tables (Gbyte size) for example. It should help with industrial automation a lot.

  10. Anonymous Coward
    Anonymous Coward

    I only open reg articles to read the comments...

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