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back to article Intel, Sun vet births fast, inexpensive 3D chip-stacking breakthrough

A startup headed up by former Intel chip architect, Sun Sparc CTO, and Transmeta cofounder David Ditzel has developed a way to allow communication in 3D stacked chips without the expense and fabrication hassles of creating physical connections between the layers. ThruChip Communications' ThruChip Interface (TCI) uses inductive …

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  1. John Smith 19 Gold badge
    Meh

    Wow. NFC *finally* finds an actual use.

    No doubt the "bolt on" nature will appeal to designers and mean designs can be moved between foundries a bite easier.

    Obvious questions would be.

    Do you feed the signal straight to the coil or is there some kind of protocol involved?

    If so what's the overhead in bits per block of data (which could be 1 bit) being transferred?

    What's the spacing limit between coils on the same chip to avoid interference?

    And (perhaps the least checked of all) what's the maximum range that signal can go through? It should be a little over 1 chip thickness, but with 3D stacking I think some (all?) mfg's "thin" the chips to pack more in a standard package. So you could have vertical cross talk.

    Yes it's clever.

    But clever <> better.

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    1. Robert Heffernan
      Reply Icon
      Boffin

      Re: Wow. NFC *finally* finds an actual use.

      By the circuit diagram and signal trace image in the article it looks like there is no protocol involved. The sender is simple it just charges a coil on the high signal and discharges it on a low.

      The receiver is a little more complex, when its coil pulses positive in response to the charging of the senders coil it sets a flip flops output to high. When the senders coil discharges the receivers coil pulses negative which is used to reset the flip flop which then outputs a low.

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      1. Alan Brown Silver badge
        Reply Icon

        Re: Wow. NFC *finally* finds an actual use.

        There has to be a protocol of some sort, otherwise a string of 1s or 0s (or an asymetric ratio of 1s/0s) will cause problems.

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        1. Michael Wojcik Silver badge
          Reply Icon

          Re: Wow. NFC *finally* finds an actual use.

          There has to be a protocol of some sort, otherwise a string of 1s or 0s (or an asymetric ratio of 1s/0s) will cause problems.

          See itzman's comment above: all that's needed is an encoding such as NRZ or Manchester. Those aren't typically held to constitute a "protocol"; they're ways of indicating bits on a carrier, not arrangements of bits (which is what "protocol" usually covers).

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    2. itzman
      Reply Icon

      Re: Wow. NFC *finally* finds an actual use.

      shoulkd be no need for error connection and what matters in terms of crosstalk is the nearets of te intended receiver to the farness of the unitended

      It is simply a (chip) cored transformer.

      What it cant do of course is nramsmit DC, but that needn't be an issue - a simple 'in phase with master clock' is a one state and out of phase a 0 state etc etc.

      Plenty of encoding technologies like NRZ or Manchester can use an 'AC' transmission medium to transfer 'DC' states.

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    3. Michael Wojcik Silver badge
      Reply Icon

      Re: Wow. NFC *finally* finds an actual use.

      NFC (aka "induction radio") was allegedly used by the team that created the "shoe computers" to predict roulette outcomes, according to Bass' The Eudaemonic Pie. And that was circa 1980.

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  2. Anonymous Coward
    Anonymous Coward

    Yes but what about supply voltage to each layer..

    ..are these passed via induction too? If they are going to still have a connection on each layer then why not go completely capacitive instead and cut down on the number of channels you have to keep away from your main clock

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    1. Robert Heffernan
      Reply Icon

      Re: Yes but what about supply voltage to each layer..

      No, the power supply for each layer is done with conventional wire bonding, which for a few power wires around the edge of the die. The power wires can be done during the placement and bonding of each wafer.

      The website has diagrams of how this works, they place the base die, put a layer of glue, align the next die on top, bond the power wires, put a layer of glue which encapsulates the power wires, places the next die, etc.

      The upside of this approach is that there are only a few power wires per die (dependent on power consumption) which are bonded using existing low cost reliable technology. You aren't trying to make hundreds or thousands of connections between each layer using a new and extremely precise technology which increases manufacturing costs.

      I can see a potential side-channel attack to this though.. what is the possibility of reading the inter-layer pulses externally to the chip?

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  3. Bartholomew

    EMP

    So EMP weapons will be more effective in the future ? Also a changing magnetic flux will give rise to RF signals, it looks like these chips will need metal Faraday cages to help block Tempest monitoring or pass FCC standards - whichever is more important.

    On the bright side there may be so much RF generated by these chips to make Tempest monitoring so costly as to be ineffective.

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    1. Destroy All Monsters Silver badge
      Reply Icon

      Re: EMP

      If that is a problem it means you dump most of the energy going into the chip out into the aether.

      Hopefully not.

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  4. Ken Hagan Gold badge

    Nit-pick: I wish the article had mentioned the physical size of a link and the achievable data rate.

    Fortunately, both numbers appear to be on the linked website: 15 microns and 10Gb/s.

    (Aside: The idea looks like it solves a long-standing problem of real commercial value using only technologies that could have been deployed years ago had anyone thought of using them in that way. It is therefore exactly what the patent system ought to be protecting: provably non-obvious inventions).

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    1. Bronek Kozicki
      Reply Icon

      Shame there is no latency figure anywhere. On the top picture there is visible time shift between Tx and Rx , I wonder what it is. Asking because in some applications, latency is the killer (e.g. if we were to ever get stacked MRAM chips with latencies no more than low tens nanoseconds ... yum)

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      1. itzman
        Reply Icon

        Re: latency...

        almost certainly teh whole shebang will be clocked synchrnously with a matser clock being used to 'decode' the sort of serail data rates. So 64 of these little transfornes in parellel would represent a one half clock cycle delay at worst.

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  5. John Savard

    Sun

    I remember an announcement a while back from Sun that it had developed a similar technology, but they were using it not for stacking chips on top of each other in a pile, but for putting chips side by side (although the even chips rested on top of the edges of the odd chips, as the contact was surface to surface as in the 3-D version).

    It had the limitation that while it was better than driving the signals off-chip normally, it still wasn't as good as just having a single chip; there was still a big delay and a limit on bandwidth. But if you could group your functions well, it solved the yield problem without having to keep up with Intel in advancing process technology.

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    1. Ken Hagan Gold badge
      Reply Icon

      Re: Sun

      Interesting. That would presumably count as prior art.

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  6. ecofeco Silver badge

    Clever clever

    Well I'm impressed.

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  7. Hugh McIntyre

    Not the first ...

    This type of thing has been reported before - for example ISSCC 2009 paper 13.5 reports on a scheme by Kelo University and the University of Tokyo for inductive stacked signalling in a stacked NAND flash product (Like this design, they also used wire bonding for power). And the 2009 paper lists prior art references back to 2004 (also at ISSCC).

    Also note that the CTO Tadahiro Kuroda listed in the article was also one of the co-authors of the 2009 paper, so presumably the startup is linked to the earlier research.

    I've not checked the details to see if TCI's design is better than the previously reported research, but this is not the first time this type of thing has been reported. Whether it takes off instead of TSVs remains to be seen...

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  8. kit

    Does its performance still hampered by signal noise and the speed of the signal processors? If so , I recog it as an intermediate solution with respect to real TSV

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  9. Fruit and Nutcase Silver badge
    Alert

    Core temperature

    now engineer a way to get that extra heat out

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    1. Alan Brown Silver badge
      Reply Icon

      Re: Core temperature

      I's say "heat pipes", but someone's probably already done it. (We use them fairly extensively in space kit. Convective cooling isn't an option in a vacuum)

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    2. Nigel 11
      Reply Icon

      Re: Core temperature

      It's not necessarily a problem. An actively cooled CPU can dissipate ~100W emanating from a square centimeter of silicon. So if the chips you want to stack generate 1W each, you can stack them 100 deep before the problem's much harder than a CPU. (Somewhat harder because you need thermally conductive glue between the layers, and thermal stresses must not destroy the assembly or the individual chips).

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  10. ShortLegs

    Remember the chip used by the T800, and examined in T2? One step closer to Skynet ;)

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    1. Destroy All Monsters Silver badge
      Reply Icon

      It's not this chip.

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