Storage crumblies, newbies race to push out flashiest gear

Perhaps the following statements (shown at bottom of this comment) were written in haste but there are a couple of issues regarding the HDS flash announcement;

1) 4x sustained throughput@500MB/Sec x 4 = 2.0GB/sec, not 2TB/sec.

2) An SSD is a storage device, not a controller, so a direct comparison is spurious.

3) Throughput in itself is a poor metric for characterizing flash performance; IOPS would be more useful.

4) 1 Million x 8KB IOPS with a flash-based VSP is not that impressive when compared with the number of IOPS that can be supported by much smaller and considerably less expensive subsystems that are already commercially available and installed today.

In particular HDS says the controller will have:

---

4 x sustained throughput of current MLC flash SSDs;

---

With good MLC SSDs offering 550MB/sec and 500MB/sec for sustained read and write operations, the HDS controller should have a 2.2TB/sec and 2TB/sec sustained read and write bandwidth level.

VSP does more than million IOPS

An HDS spokesperson sent this information to me:

>>>>>>>>>>>>>>>>

One thing I noticed though in your article that I was hoping could be corrected is the following statement: “Virtual machine density with a VSP can be doubled. HDS says an all-flash EMC VMX 40000 does 810,000 IOPS, about 20,000 less than a flash accelerated VSP.”

Our VSP with flash acceleration achieves more than 1 million IOPS, so I think the 20,000 figure above should be 200,000.

>>>>>>>>>>>>>>>>>

We should envisage a flash-accelerated VSP running at 1.2 million IOPS according to this statement.

Chris.

VSP Flash Acceleration

HDS hasn't explained how the Flash Acceleration firmware feature for the Virtual Storage Platform (VSP) will work. But they said it is a form of "express host I/O". Therefore I suppose that they have implemented a front-end to back-end director fast pathing for reading flash located data. This means a cache bypassing function, every flash read is a read hit. For flash writes the solution is not so easy, the cache must to be used as write buffer. The VSP has an internal PCI Express switching network which connects the front-end directors (FED), the back-end directors (BED), the multiprocessor packages ( aka virtual storage directors VSD ) and the cache boards. Normally the VSDs establish data connections between the cache boards and the FEDs or BEDs. But it is possible to create direct FED-to-BED connections for synchronous read I/O from flash. The EMC VMAX cache-based ( NUMA ) method for VMAX engine coupling can not support the fast path approach, HDS has here a clear architectural advantage.

VP Marketing

Correction. The NexGen guarantee does apply to any hybrid using solid-state in disk drive form factors so Tegile, Tintri among other start-ups are included.

Posting IOPs and capacity to spec sheets is easy, delivering under non-ideal workloads in a real environment is another matter. We look forward to being called out on our claims.