back to article Give Samsung a hand: Chaebol pulls back Arm to strike Intel's chips

Samsung has said its chip foundry building Arm Cortex-A76-based processors will use 7nm process tech in the second half of the year, with 5nm product expected mid-2019 using the extreme ultra violet (EUV) lithography process. The A76 64-bit chips will be able to pass 3GHz in clock speed. Back in May we wrote: "Arm reckoned a …

  1. wurdsmiff

    Are there notebooks powered by low-end Xeons?

    "general notebook users won't notice performance differences between Arm and low-end Xeon-powered notebooks."

    Is this correct? New, mobile workstation-class ARM chips would be insane. New, low end Pentium beating ARMs would be cool, but not quite the same.

    1. Dave 126 Silver badge

      Re: Are there notebooks powered by low-end Xeons?

      There are some mobile Xeon chips, but none aimed at 'general notebook users'.

      If this isn't a mistake, then maybe the author can add a sentence to the article to clarify things.

      1. JassMan Silver badge

        Re: Are there notebooks powered by low-end Xeons? @Dave 126

        See this. Ok its not low end but it sound like a Samsung/Arm could soon be giving it a run for its money and waste considerably less power in the process. ie a true notebook rather than a desk mounted portable unless you like incinerated kneecaps.

  2. Anonymous Coward
    Anonymous Coward

    Just need a powerful GPU to go with it called "leg", can't see it being cheap though.

    1. BeerTokens

      I believe this is the link you are looking for...

    2. onefang Silver badge

      'Just need a powerful GPU to go with it called "leg"'

      I don't think that would stand up.

      1. Anonymous Coward
        Anonymous Coward

        An amazing feet of engineering all the same.

        1. gotes

          It would be very handy.

    3. Tom 7 Silver badge

      Re Leg

      I'm assuming the GPU is for something other than graphics? I'd be seriously interested in some 7nm ML ARM stuff in my 'laptop' - that's doing 3TOPs per W at 14nm so it would be like having a Titan with no interest in my battery on the move!

  3. Anonymous Coward
    Anonymous Coward

    Would be very, very interested in seeing what the standby power consumption is like on those chips as down at that size, current leakage starts to dominate, you can have real trouble actually turning anything off, primarily due to quantum tunnelling and thermal effects.

    It can also really affect reliability, process tolerances are insanely tight and, as you're already operating at the limit, a tightly controlled gate can still have false switches due to the aforementioned quantum tunnelling and thermal effects. Once you combine process drift with them, you find the percentage of gates performing unpredictably can rise significantly.

    Not showstoppers, but a huge engineering challenge.

    1. DougS Silver badge

      Reduction of leakage is why we have fins and later gate all around transistors.

  4. alain williams Silver badge

    Please can we stop comparing CPU speeds by clock speeds

    It is bad enough when we are talking about CPUs that implement the same instruction set, but with something different the numbers are largely meaningless. This is why we have SPEC, and even that is not simple.

  5. Morten Bjoernsvik

    arm servers out there

    I would love to replace my aging Xeon E5540 with 4cores and 192GB of ram (Initially from 2011) with some arm iron. Atleast some competition will give us better prices.

  6. onefang Silver badge

    Intel are Mostly 'Armless.

  7. Stuart Halliday

    With a RISC processor taking an average 2 clock cycles per instruction, against a CISC of 20 CC/I.

    Am I right in thinking it'll be a darn sight faster at 3GHz than anything Intel can do?

    1. Anonymous Coward
      Anonymous Coward

      > ... CISC of 20 CC/I.

      Where are you getting 20 clock cycles per instruction from? That seems badly off.

      1. Anonymous Coward
        Anonymous Coward

        Besides, Intel CPUs these days are hybrids. Their instruction timings are highly variable, able to go quickly for simple instructions, and spreading out when you start getting complicated or need to dig into the memory. I don't believe any other architecture to date is all that different, as the main stumbling block is the complexity of the instruction itself. An architecture that doesn't have a complex instruction simply has to make it up with a bunch of simpler ones, so it's a wash that way.

        1. Mage Silver badge

          Intel CPUs these days are hybrids

          Yes, some have RISC cores.

          Also "RISC" is a misnomer in many cases, as there may not be a reduced set of instructions. Most "RISC" architectures are better called Load/Store architectures with aim to do any instruction in one or two clocks.

    2. Kevin McMurtrie Silver badge

      All high performance CPUs have some kind of execution pipeline where the end result is at least one instruction completing per clock tick. Longer pipelines in CISC do vastly increase complexity but Intel has the resources to fix some of those problems. Not all, as recent news shows.

      1. Tom 7 Silver badge

        @Kevin . pipelines

        And it seems these are full of problems with uncleared memory. I wonder how many pipeline paths will be de-utilised due to potential memory leaks.

    3. Anonymous Coward
      Anonymous Coward

      CISC of 20 CC/I

      x86 has been superscalar (<1 CC/I) since Pentium 1 in 1993.

  8. ATeal

    About the RISC stuff

    It's usually 4 cycles per instruction, but it's the "classic RISC pipeline" where 4 are on the go at once, so really "1 per cycle" with little exception.

    You can go a bit further if you interleave load/store with reg-to-reg instructions (or provide them interleaved) and do 2 at a time. Unfortunately (AND I'D LOVE TO BELIEVE ME) - I have no experience optimising or looking at dissassemble stuff for such hardware.

    But yeah "classic RISC" with "double" that stuff with the load store interleaving can do 2 instructions / cycle throughput sustained.

    It might be a 5 step pipeline, but throughput remains. And this includes the bubble hazard shit workarounds you can do.

    I think this example might be mips, it's the one without the branch delay slot. It's the classic Undergrad textbook "Computer organisation and design - the hardware/software interface" (there are so many) - it's on my shelf.

    -----ADDENDUM with stuff I *do* deal with------

    Check out this filthy porn site:

    The best you can hope for is to keep each port going per cycle and Skylake has 8 I think. I deal with SandyBridge mostly though.

    Don't get me started on how they've fucked up AVX.

    But yeah the 6 ports are your (probably widest so anti-)bottle-neck with issuing stuff. As much as I'd love to show off, but I don't have time:

    SandyBridge can have a surprisingly high amount of instructions inflight, but it has to retire/commit them in order, best you can hope for is 6 (4 ops, but they can be fused).

    Decoding is the biggest issue with x86-64 stuff, as a rule of thumb it costs you 40% in something, be it power, die area (of the actual core of the core), or performance if you neglect it, and that's why Intel never stood a chance w/ phones/tablets.

    I'd really love to show off because "good with computers" sounds like I can set up a printer, but trying to rush it makes me look like a noob quoting from a presentation, read the page. [removed "joke" about what "this stuff" is to me]

    BTW total in-flight issues is between 100 and 200 as a "rule of thumb" - this works well because of the variability of what even your "common" compiler-generated instructions do WRT "uops" and shit.

    You have to dig deep in manuals and have very specific bits of code to talk about and write a kernel module to poke with and set up special performance registers - it's a mess. So it's not really worth looking for more than this rule.

    LOL no wonder spectre happened!

  9. ForthIsNotDead

    ARM business model

    This is where ARM gets to reap the benefits of their business model. The pain of producing their designs at the latest 5nm size is somebody else's problem to a large extent. Intel, on the other hand, build their own fabs to produce their chips, so they need to get the RoI before they can upgrade. Intel, ultimately, are doomed I feel.

    1. Charles 9 Silver badge

      Re: ARM business model

      If that were so, AMD would've eaten them for lunch already. I suspect there are benefits to vertical integration (in this case, Intel having their own fabs), be it quicker turnaround or a better ability to adapt to conditions (recall that it was AMD that was first to x64 with the Opteron, but Intel--with its in-house fabs--managed to leapfrog and keep well ahead of AMD for at least a decade).

      I will admit that Intel's instruction set is both gift (allowing it to support more software than just about any other architecture out there) and curse (supporting all that stuff entails carrying a lot of baggage), but they're also kind of stuck with it which is why they've more or less dropped their work on alternative processors (including ARM). The fact they're IINM still the go-to architecture for performance applications also gives them a leg up on any other non-x86 architecture that wants to try to support that kind of software (since any kind of emulation, such as Qualcomm's attempts, are probably going to really stink in performance-intensive applications).

POST COMMENT House rules

Not a member of The Register? Create a new account here.

  • Enter your comment

  • Add an icon

Anonymous cowards cannot choose their icon

Biting the hand that feeds IT © 1998–2019