# Second time's a charm? WD tries again with 3D NAND, doubles capacity

WD is firing up an early production run of its 512Gbit 64-layer 3D NAND chip at its Yokkaichi, Japan, foundry, with its partner Toshiba. The silicon uses a triple-level cell (TLC) flash design, which stores three bits per cell. Progressing from this pilot job to mass manufacturing will take at least six months, so don't expect …

"...triple-level cell (TLC)....which stores 3 bits per cell."

Three bits? Then that'd be an eight-level cell.

Three levels? Initially I thought they would be for 'True', 'False' and 'Mu' , but Wikipedia tells me it is a four-bit-per-cell (16 levels) device to allow for all that error correcting cleverness that's needed here.

Yes. I too need a beer after trying to get my head round all that.

Wouldn't you normally have 1 bit per cell? Therefore 3 bits per cell would be triple a 1 bit per cell structure.

>2460 Something:

"....SanDisk X4 flash memory cards are based on NAND-memory that stores four bits per cell, using 16 discrete charge levels (states) in each individual transistor." [from my wiki link above]

@ColonelDare

My take on that excerpt (and I have read the wiki article as well) was that the SanDisk X4 is using 4 bit cells, Samsung are using only 3 bit cells. Either way, my original response was aimed at JeffyPoooh rather than yourself :)

@JeffyPoooh

I understand binary, however I still think your misunderstanding (or just making a joke?) the concept. A single bit has 2 states, either on (1) or off (0), this is a single layer cell (SLC), despite the fact that it has 2 states, it is still a SLC not a 2 layer cell. By creating a 3 bit cell, they are correctly referring to it as a triple layer cell (TLC), as it is 3 times the bit capacity of a SLC. Yes it allows for 8 different states as each bit can still be on or off (000, 001, 010, 011, 100, 101, 110, 111) however it is still 3 bits vs 1 bit. Hence TLC vs SLC.

Apologies if you were going for sarcasm/joke, it didn't come across.

@2460

The only intended joke was the "Decimal 5" = Binary 101. (<- that's actually hilarious)

The basic issue is that "level" in this context means voltages. It doesn't mean physical levels. A so-called "Triple Level Cell" is just *a* (singular) cell (ONE cell storing ONE voltage). They use EIGHT different voltage LEVELS to store the three bits.

That's the point of the Industry Standard misnomer.

A TLC is actually an 8LC storing 3-bits.

The problem with their naming scheme is that they've left themselves an ever-increasing gap in their poorly chosen scheme.

One could imaging that the maximum number of voltage levels isn't a power of two. But the data could be smeared over several cells. Their naming scheme leaves no room for this obvious intermediary technology.

They should have invited me to the meeting. All this is obvious.

Instead of storing an on/off bit, they store one of eight different voltages in each cell.

One of eight levels stores 3 bits.

And I'm *not* going to explain that last part as it's "Decimal 5" (= "Binary 101"). LOL

You are confusing "data" with stored states. 3 bits = eight different stored states in the memory cell. Just like MLC (2b/c) = 4

TLC is triple level cell: three bits are used to data in eight levels (000, 001, 010, 011, 100, 101, 110, 111). Blame the flash industry for the slightly odd naming.

C.

2. The attached graphics shows Tb/in2. I believe this is incorrect as is should be Gb/in2. Intel/Micron recent announcement of their 256Gb 64L states 59mm2. I believe this = 2799Gb/in2 not 2799Tb/in2. Please check the math.

1. #### Re: nvm.expert

Yup, the graph was wrong - we've torn it out. Don't forget to email corrections@theregister.co.uk if you spot anything wrong.

C.

## POST COMMENT House rules

Not a member of The Register? Create a new account here.