"It's extremely tricky using 193nm UV light to construct transistor gates smaller than 22nm, let alone 7nm"
20 years ago the Great White Hope was x-ray lithography. I guess it could still be on the back burner.
ARM and TSMC today announced they are working together to make chips featuring 7nm FinFETs a reality. This follows on from their work on 16nm and 10nm FinFETs. Taiwan-based TSMC describes itself as "the world’s largest dedicated semiconductor foundry," and it churns out chips for the likes of Nvidia, AMD, Qualcomm, Apple, …
Mostly because actual Xray photons (defined as between 10 nm and 0.01 nm wavelength) were found to knock loose too many electrons in the resist material and cause fuzzy edges, negating the minimum feature size gain. This is still a problem with EUV (13,5 nm wavelength) but to a lesser extend.
I either write too technical or too simple, judging from comments. With millions of readers, it is impossible to please everyone. If you know how transistors work, you don't need my article :-)
If you're skimming El Reg for news and can't remember or don't know how semiconductors work, I hope this has helped.
There isn't a standard for what constitutes an "x" nanometer process. It is likely that Intel's 10nm will be pretty similar to TSMC's 7nm so if they are out of the gate at roughly the same time then all it will mean is that the foundries have finally caught Intel (thanks to all the smartphone SoC revenue) and not surpassed them.
EUV is coming. Development is further along than you seem to imply here. Yes, it has taken much longer than expected but when you are fighting the current limits of many many fields of physics and chemistry things don't always go as planned.
Many, many new techniques and processes have been developed just to make EUV a reality. Working tools now exist and are being used for development.
I work in this particular field. If I look over my left shoulder I can see 2 EUV sources being assembled right now in fact.
I know its been a while but maybe you still read this. Throughput is currently a company secret but lets say sufficient for proto run production, with full production speeds in the pipeline very soon. Wafer size is standard 300mm (noone is planning a 450 fab so no point in building a machine for 450mm. Logistics alone at that size become a challenge). Powerconsumption is again a company secret but relatively high for the actual EUV light power actually reaching the wafers. (kWatts in hundred something Watts out.)
Sorry I can't be more specific. NDAs are a pain.
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