A few clarifications
It is called 3D memory because bits can be stacked. As shown in your drawing, it is presently at 2 bits high. (This is what they meant by "two layers" not that there are only two layers in the fabrication process.) Bit stacking can be done because the storage is not making use of the single crystal silicon substrate. As long as they can access the various layers of word and bid lines, they can keep stacking the bits.
There ARE transistors on the chip. They are NOT in the memory cells but will be around the perimeter to decode the address, read the signals from the bits and convert them into the appropriate output voltage and send the appropriate signals to write bits. (Although the chip is random access, they will almost certainly read and write Words and not single bits.)
The reason a resistive memory cell can be scaled down farther than present memories:
•DRAM storage depends on the area of the capacitor to store charge. If the area gets too small the amount of charge becomes harder to detect.
•Flash depends on charge of a floating gate. Again, as the gate gets smaller the amount of charge is limited and you have to move it closer to the channel of the transistor (thinner insulator) to modify the threshold voltage. If the gate is too small and the insulator too thin, small amounts of leakage can degrade the storage time.
•A variable memory material will have the same ratio of Low to High resistance no matter how small the bit is as long as the cross sectional area and thickness of the storage volume keep the same ratio as it scales down. It is possible, depending on the resistance change mechanism, to have a lower size limit. For example, phase change memory could be limited by how large the bit must be to exhibit crystalline characteristics, since the surfaces of the volumetric bit will be influenced by the materials on which or to which it is in contact and not be crystalline for some skin depth.