Re: More to the story....
I would have to take exception to at least one of the points you make reference to in your paper
'Using Storage Class Memory for Archives with DAWN, a Durable Array of Wimpy Nodes'
"Even assuming data is overwritten daily, it would take over 25 years for a conservative write endurance of 10,000 cycles to be ex-ceeded . Of greater concern are the issues of read dis-turb and data retention. "
The only mention I can see of 10,000 is related to 'latency' tests.
'Empirical Evaluation of NAND Flash Memory Performance'
Which goes on to state ( in the next paragraph):
"Due to the high variance of the measured endurance values, we have not collected enough data to draw strong inferences, and so report general trends instead of detailed results."
More of an issue, it the fact that since this was a 'latency' test for device speed, the writes & reads would have been in a highly compact burst on a 'new'ish chip. ( even the de-soldered devices)
They state they measure "3.2 Endurance " by:
"Program/erase endurance was tested by repeatedly pro-gramming a single page with all zeroes, and then erasing the containing block. Although rated device endurance ranges from 10^4 to 10^5 program/erase cycles, in Figure 5 we see that measured endurance was higher, often by nearly two orders of magnitude, with a small number of outliers."
So basically this 10,000 writes was performed in a burst with values of 00 & FF ( Nand flash erases to FF)
which is not a true test of an MLC device, since the test is only testing 2 of the possible 4 states the cell can store AND the test is angled to minimize read/write disturbs from adjacent cells, not to mention the two BEST values for the read/write amps. to pick out. ( I say that because the author appears to be fully aware of how MLC devices function(2.1) but uses a 'non-standard' representation for his test data all '1' or '0')
There is also no mention of:
1. The Block number they choose, in their 'single' block test ( that result seems to make me think it was block 0, which all manufacturers give the highest R/W rating to)
2.The ambient conditions the tests were performed at.
3. No mention of the Read ID's of the chips tested in . ( manufacturers part numbers on the case are NOT an indication of the enclosed die, they might have been all from the same manufacturer)
I would 'like' to have seen the endurance data 'test' performed with a range of test data
1. 'True random data'
2. 'Marching ones'
3. 'Marching Zeros'
Really I would have expected a far better testing regime from the paper, I would have some concerns about the conclusions.