"May the best chip – or chips – win."
Fascinating developments. Those who have recently been proclaiming the death of Moore's Law may have to think again.
Samsung has announced that it has begun volume production of what it characterizes as "the industry's first" vertically stacked NAND flash-memory chip. Samsung's mass-produced 3D vertical NAND (V-NAND) chip Behold the industry's first mass-produced three-dimensional NAND flash chip (click to enlarge) "Following the world's …
Moore's law still doesn't apply, the feature size hasn't reduced they've just stacked more wafers in a single chip.
Any cost saving from doing this is down to fewer parts to be soldered which, as it's all automated, is naff all.
I'm not sure what the point is. It's not like flash drives are short on real-estate. I for phones there's a gain in having a single chip. So it's not that exciting a development.
Actually the 18 month time frame was a different Intel CEO predicting that chip performance would double due to more, faster transistors.
Moore's law was an observation that the number of components on integrated circuits had double every year since . . [a date I cant remember] until [another date I can't remember] and would continue to do so for [a period that I don't recall but is somewhere between 10 and 20 years].
Assuming you're serious ...
That's a development or presentation DIL (dual in line) package. The window allows you to "see" the die.
Back in the 70s chips actually looked like that, of course, but these days chips are packaged in much smaller devices - like the ones at the top of the page - where the gap from contact to contact is approx 0.5mm instead of 2.54mm in the DIL package.
The main use for windowed packages like this in years gone by was to allow you to UV erase EPROM before EEPROM and flash came along (these are electrically erasable, so no need for a UV eraser).
"That's a development or presentation DIL (dual in line) package. The window allows you to "see" the die."
I was totally correct then (apart from exact terminology). I do remember UV EPROMs and sticking thick black tape on top after they'd been programmed, 'just in case'.
It’s not even a “prototype marketing” package its just something the graphic designer has created to look nice.
The clue is complete absence of bonding wires – between die and package – and from the die in BGA packages I have cut apart the connection points are in fact on the reverse side of the die making it impossible to mount in a ceramic dip package.
...is how the new devices differ from existing technologies in terms of write durability. Samsung talk about reliability, but this could equally well refer to whole-device failure: they make no assertions about the mean time before failure per cell based on number of write/erase cycles, and this raises my suspicions.
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