This idea is far from new.
However, in the past electron-beam 'masking' was always considered much slower hence more expensive. It'll be interesting to see how it scales up now that's it's become forced on the industry.
An international consortium of chip boffins has demonstrated a maskless wafer-baking technology that they say "meets the industry requirement" for next-generation 14- and 10-nanometer process nodes. Current chip-manufacturing lithography uses masks to guide light onto chip wafers in order to etch a chip's features. However, as …
in the equipment used to etch a pattern on silicon. Quantum tunnelling is how the uncertainty principle manifests as electrons travel along ever-smaller circuits. As you shrink circuits and the overall energy levels approach Planck scale (which might be measured in terms of energy gaps or distance) then it causes electrons to apparently "teleport" at random, so smaller circuits introduce quantum glitches.
If you're talking about the actual process by which circuits are etched, however, you're probably talking about very high energy beams (x-ray lithography or, in this case, an electromagnetically accelerated electron beam) then the energy of the photon (x-ray) or electron (CRT-like accelerator) can be ramped up to a level where they're well in excess of the Planck-scale energy levels, so won't be as affected by the uncertainty principle.
There are still problems, though. Even x-ray lithography (higher energies relative to UV) mightn't have enough energy to cast a clean shadow against the mask--hence (I take it) the need for multiple masks and x-ray sources. As for CRT, aiming is still hard at high energies due to the need to have a very high frequency circuit for steering the electron beam. Aiming has been a problem with CRTs since the beginning. The traditional solution (to get the electron to hit the right pixel) is to have a charged mesh close to the target which helps to focus electrons that are slightly off-target or absorb those that are more wildly off. Higher-energy electron beams probably do something similar.
The designers of these kinds of etching hardware still have to worry about the uncertainty principle as they get to ever-smaller scales, but the physical description of their problems manifests more as wave/particle duality (inability to cast hard shadows due to edges causing a diffusion/diffraction of the beam) than quantum tunnelling per se ("teleporting" low-energy electrons in a circuit). At least, that's how I understand it...
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e-beam lithography has lots of benefits, but it is extremely slow. This technique increases its speed by a factor of 10,000 by using parallel beams.
The article points out one advantage: you no longer need to create a mask, and the cost of the mask is drives the cost of the photolithographic process. Masks have become extremely challenging as feature sizes dropped below the wavelength of the light used for the photolithography: the mask is no longer a simple reproduction of the shape of the desire result. Rather, the mask (rather, the masks, since "double-patterning" is needed) have funny shapes that cause the light to interact with the surface based on the rules of optics,and not all desired results have corresponding masks.
But there is another consequence that is even more important: A mask is so expensive that you must produce a huge number of parts to amortize the mask cost. For E-beam, you can spefiy the exact result you want, and the beam can produce that exact result. But even more importantly, there is essentially no penalty for creating multiple different kinds of devices on the same wafer. This completely changes the economics for creating experimental devices and for small production runs of ASICS, and it allows the industry to re-open the idea of wafer-scale integration.
E-beam failed because is was too slow, and it lost ground to photolithography as the wafers got bigger and the feature sizes got smaller. But suddenly we have parallel e-beams, which conceptually increase the speed by number of parallel beams (currently 10,000.) But if 10,000 now, why not 1,000,000 in the future? We get to the point where a specialty fab could produce a single instance of an experimental custom device for not too much extra money, and suddenly we can create a small quantity of ASICs for $100 apiece.
Small runs become much more interesting this way. Ultimately, one might envisage chip making to be commoditized like 3D printing is becoming a commodity. One off parts are becoming affordable (see LOHAN). Imagine designing your own ASIC chip from scratch rather than going the FPGA route. Design a schematic, send it off, have a wafer-full made, mounted and sent to you.
Far fetched now, but maybe some day.
What do you mean "a man can dream"? A man should dream!
Whilst I admire your enthusiasm for this tech, I have just had the 80's on the phone and they want their design methods back!
Not used a schematic for chip design for at least 15 years (strangely it was the Japanese office that still used them, bizzare if you ask me!). All VHDL/VERILOG/C these days (cut down version of C) depending on the application.
not forgetting the fact that you could also build multiple "heads" to write each section in parallel,
or why not cut down the size of wafers? Bigger wafers helps when you have fixed masks, but does the same rule of economics need to apply to e-beam lithography? If you had smaller wafers you might conceivably create circular chips from <1cm radius chips that are printed by a circular format beam. Many wafers per second could fly through the machine like coins through a slot machine. Move the wafer not the head? One wafer per chip but at such a rate that you get charged just for set-up, chip quantity, packaging and logistics.
At this point volume becomes not a question for the fab, but a question for the designer, can you afford the set-up and logistics for your short-run chip? Yes, then go ahead order a tray of chips, makes no difference to the robot overloard controlling the production line. Fab-less chip companies could just license designs to their customers and sell them support/consulting services, rather than messing with the commodity cost of chip printing. Economies of scale then get pushed to the integrator who can get volume discounts from the fab because of good forecasting, single set-ups and cheaper logistics.
"Direct write" has been around since the early 80's and direct electron beam lithography was tried on a *commercial* scale by Electron Silicon Structures (ES2) offering a niche small scale production/rapid prototyping service. AFAIK the company went out of business but I'm not sure why. The *theory* was sound but I suspect their management made 1 or more mis-judgements.
BTW the *multiple* electron beams idea is *not* new either.
SRI at Stamford were demonstrating how a single electron beam could be accelerated to high energy and then *split* using (IIRC) a wire mesh into about 20 "beamlets" in the early 80's. However while the *concept* has been around that long it's not clear from the animation how they make it work (some sort of side illumination seems to be involved and it's not clear if the beamlets are under *individual* control, which would be unnecessary in a production application).
Note in the 80's the *big* hurdle was 1 micrometre (people were saying X-ray is the only way even then). So the linewidth has gone down by 50 but (it appears) the number of beams has gone up by 50 000. OTOH the wafer diameter also doubled (roughly 6" ->12" for SoA lines and rising. 320mm is in sight)
So at present this needs a x300 improvement in speed versus a x60 speedup for EUV.
FPGAs are all the rage in sophisticated application fields these days, because they allow for very quick design-to-product cycles.
If this technology really works, custom chips can be made at much lower cost and their system performance is as good as a traditional ASIC. That would definitely change the landscape of the electronics industry. Create a chip using VHDL, verify it and then upload the design to electronbeamFoundry.com and three days later you have a high-performance chip ready for soldering onto a PCB !
Yes, I can see this working well. For reason that you will know well I think
1) ASIC much faster than an FPGA, easier to do higher clock speeds or lower flip flop count.
2) ASIC not so prone to single event upsets, good news for space and areo sectors
3) Cheaper to a small run of a couple of wafers, all that may be needed for an aeroplane part, as you only tend to make a few thousand planes, not millions. Cost not such a big factor if only a couple of hundred dollers per chip.
If you have shares in Xilinx or Altera or Actel etc it may be a good idea to keep an eye out for this....
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