Talk is cheap
When Intel actually delivers what they claim they can, then we'll see what is reality.
According to an article in today's EE Times, Intel will "extend its lead over AMD, IBM and other microprocessor vendors" at next week's übergeekfest, the 2008 International Electron Devices Meeting (IEDM) in San Francisco. Specifically, Intel will present papers that detail the company's latest advances in high-k/metal-gate …
or actually on their payroll? If you'll happen to look at the second entry listed under Related Stories you'll see: "Intel to present 32nm chip while AMD shows off 22nm part."
I don't mind the "Gosh! Wow!" tone of this piece so much as I mind the fanaticism. As a journalist you shouldn't be on anybody's "side".
Their chips need more transistors to do the same amount of work as other chips which is why Intel chips routinely drown more polar bears than the competition.
But as for technological innovation: it's still almost always IBM that comes up trumps with the really interesting stuff.
Fair play to intel. The whole metal gate High K dielectric problem is a really really big one. The reliability of the dielectric is of special concern. You can't use any old common or garden Hafnium oxide mush as your insulator.
The fact that intel have solved this, is a major achievement.
I think Mr BLoad doesn't seem to understand the concept of the C=kA/D he's spouting.
One should be very careful about calling people Ctards when you clearly don't understand what you're talking about.
Intel are not playing around with D (thickness of the oxide).
In a 45nm process or 32nm process the oxide is already as thin as it will go. The oxide is only a couple of 10s of atoms thick. You can't go thinner, that's it, finito. If you go thinner the oxide does not behave like it does when it's thicker. At these thicknesses quantum effects kick in and electrons can jump across the oxide without it breaking down and the leakage current goes through the roof. So unfortunately D is fixed.
A or the area gets scaled down when you go from 45nm process to 32nm process etc otherwise what's the point. In order to maintain a useable capacitance then the only factor in the equation that can be adjusted is "k". Which is changed by using different materials for your dielectric. That's why they're call high "k" materials, as the "k" factor needs to be increased.
Hafnium metal gates are required because the speed of operation of the transistor is a factor of the resistance and the capacitance. Using a different metal increases speed. Increases cost too.
There are many many many papers on this stuff available from the IEEE just search. (Very technical though) I've simplified it as much as possible.
just for the record, the metal gate is made of Aluminium, being cheaper and lower resistance than the horribly expensive Hafnium. Metal simply need to conduct, and to process easily.
Hafnium Oxide, on the other hand, is rather spectacular, withstanding about 20megavolts per centimetre (cf. about 5MV/cm for SiO) - which reduces the gate leakage, and allows the gate oxide to be thinned, (a bit - the leakage through "tunnelling" sets an absolute minimum thickness, process uniformity + tolerance means we never quite get there). the dielectric constant of the gate oxide, the high-k, is not "used" its just that all the exotic oxides have a higher k than silicon oxide, and they chose to characterise the approach based on an inessential parameter.
- if they could get the same dielectric withstand with a lower k then they'd jump at it, lower k means lower gate capacitance equals faster switching.
kevin: almost right, but...
The reason 'k' matters is that the ability of the gate voltage to induce inversion in the channel depends on the gate-channel capacitance. The larger the capacitance, the greater the influence between gate voltage and channel charge. Since gate-channel cap depends on k, high k for the gate oxide is desireable. Lower gate dielectric constant means lower performance transistors.
Low-k is useful in the dielectric between wires where we really need to reduce the effect of a signal on one wire upon the signal on an adjacent wire.
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