So what's this going to be, hex core? That sounds cool, I guess. But wtf is the Hex community?
Rarely the rebel, Intel looks to shake up the processor game with a six-core chip. Some Intel slideware leaked onto the interweb shows the "Dunnington" version of Xeon arriving in the second half of this year with 6 cores. To date, the major chip makers have done two- and four-core processors, while Sun has an eight-core chip …
and a dunny man to visit each week. I always used a bucket in the bathroom as I was (age 6) terrified of spiders! My siblings and I used to mangel the traditional children's song "Have you seen the Muffin Man" to "Have you seen the Dunny Man" in all sorts of amusing (to a 6-year-old) ways.
And a bit of random Australiana to finish with:
It may be that Intel just changed freeways in its naming pattern. The problem with that is that the name 'dunnington' doesn't correspond to much. Then again in my travels, I've come across something similar:
Ah, for the days of US99W (it was the 60's, and true to form I've forgotten all about it).
is going too many, too soon. Sure, you can make a 6 core processor relatively cheap, and then pack 4 of them into one box, but there's still a hell of a lot of software out there than only runs on one.
Until they can provide a compiler that auto-magically parallelises well, it's probably going to remain like that.
"is going too many, too soon."
Maybe, but Intel learned from their previous mistakes. They believed that they could dictate the market. That where they went, the market would follow. Their arrogance hurt them.
It looks like they woke up and decided to crush the other guy with innovation. Rather than building a small speed lead with high margins, they are trying to put amd two or three years behind.
It is good for all of us, as long as they don't win and put amd out of business.
Even if a machine is only moderately busy, you can often see half a dozen threads in the ready-to-run state. It is fairly easy for the OS to spin off device driver work into other threads and all of an application's screen drawing can be spun off.
IMHO, most client machines don't do enough work for it to matter either way and most server workloads are easy to spread across cores. Niagara wouldn't exist otherwise.
There are plenty of *magazine benchmarks* that will punish a multi-core processor and Intel have to watch out for that, but if Intel did produce a chip with too many cores, they'd simply market it as a "server product" and sell it to people who knew where they could stick it.
Some comments seem to miss the point.
Dunnington will be a MP product, there's no 6-core CPU coming from Intel (yet?) to the UP and DP market.
Also, the interesting thing is that it will be pin compatible with Tigerton, so it will be a simple upgrade for manufacturers like HP, Sun and Dell, no redesign needed. (Not 100% sure about IBM with the X4 chipset?)
This will be certainly interesting for virtualization, 24 cores in a box.
There's nothing extremely exciting in this though - the real changes will come with Nehalem.
"So Intel are still releasing poorly designed cores, relying on the old 'just add more cores/cache/MHz' trick to get some decent performance. Nothing new there then."
Er, if you know of a way to increase performance that doesn't come under the three broad headings you've just mentioned, do tell.
More cores = more instructions per clock
More cache = fewer wasted clocks
More MHz = more clocks
I suppose there's VLIW (like more cores, but works for a single instruction stream), but you weren't really suggesting Intel should spend any *more* money on Itanic, were you?
Why on earth would anyone buy a four-core Tukwila when they can get a six-core Penryn?
If Dunny will fit in HP's double-height BL680c blade, that would be 192 cores per C-Class chassis. If HP can increase the memory in the BL680c to 256GB, they will have eight 24 core, 256GB servers in 10RU.
Tell me again why I need a Superdome?
Actualyl, yes there are tonnes of ways that Intel can improve their line. They really should just abandon the x86 architecture and expose the RISC cores of their chips. The horrible variable instruction length and execution time required by the Intel chips makes them extremely relient on internal register reordering, out-of-order-execution and what-not.
Removing those complex pieces of nasty would result in a much better execution profile, especially when it comes to branch prediction misses. Not to mention making it easier for compilers to optimize for the seperate execution pips.
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