Beware of 18MB cache Itanium chips
HP is dumping defective chips on unsuspecting customers. Defective Itanic chips are being sold with 25% of the cache disabled at firesale prices.
The speeds and feeds for Intel's upcoming "Montvale" version of Itanium have made their way to the web, revealing a chip far less spectacular than once hoped. According to DailyTech, Intel will ship 1.66GHz, 1.60GHz and 1.42Hz versions of Montvale under the Itanium 2 9100-series brand. The dual-core processor, due out near year …
POWERFAN's comment seems curiously naive. I very much doubt that any Itanium customer is in the least doubt about the source of an 18MB cache version. The Itanium's cache features are well documented and the fact that they can disable defective banks of cache well known. If you look at the Itanium's die it is both huge, and the level 3 cache takes up the lion's share of the area. The probability of defect inclusion is very high and the most likely failure will be in a cache bank. The idea of designing chips that can be reconfigured around defects has been around for many years, and the ability to de-configure a cache bank simply one of the easiest early implementations.
Whenever you go out and buy a processor that is not running at the maximum available clock rate you are doing exactly the same thing. Do you scream that the customer is being foisted a defective chip because it failed testing at the higher clock rate? No, the industry has by binned clock rate from the beginning. Now we are seeing the start of what will become an increasing trend - binning based upon working functional units.
The Itanium isn't the only current example either. The Cell is sold in the Playstation with 7 processors. Curious number, especially when there are 8 on the die. IBM only guarantee that 7 work, so that it what they sell you. It is possible that the 8th does too. I don't hear cries of anguish about Playstations being foisted onto unsuspecting customers with "defective" processors.
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