Re: "chose not to serve" @Loud Speaker
That's a very interesting point, one I had not thought about, but the term CISC actually refers to a Complex Instruction Set Computer, and is defined by the number of instructions in the set, and the number of addressing modes that the instructions can use. I would say that the memory bandwidth savings were secondary, especially as most early computers processor and memory were synchronous.
I'm not sure that I totally agree with the definition of a PDP11 as a CISC (although it was certainly several generations before RISC was adopted), but the instruction set was quite small, and the number of addressing modes was not massive and exceptionally orthogonal, so it does not really fit in to the large instruction set many addressing modes definition of a CISC processor.
What made the PDP11 instruction set so small was the fact that the specialist instructions for accessing such things as the stack pointer and the program counter were actually just instances of the general register instructions, so were really just aliases for the other instructions (you actually did not get to appreciate this unless you started to look at the generated machine code). In addition, a number of the instructions only used 8 bits of the 16 bit word, which allowed the other 8 bits to be used as a byte offset to some of the indexing instructions (contributing to your point about reducing memory bandwidth).
One other feature that was often quoted, but was not true of most early RISC processors was that they execute a majority of their instructions in a single clock cycle. This is/was not actually part of the definition (unless you were from IBM who tried to redefine RISC as Reduced Instruction-cycle Set Computer or some similar nonsense), although it was an aspiration for the early RISC chip designers. Of course, now they are super-scalar, and overlap instructions in a single clock cycle and execution unit, that is irrelevant.
Nowadays, it's ironic that IBM POWER, one of the few remaining RISC processors on the market actually has a HUGE instruction set, and more addressing modes than you can shake a stick at, and also that the Intel "CISC" processors have RISC cores that are heavily microcoded!