The 'F' designated processors with a UPI socket on the processor package are particularly interesting.
Intel has taken its Skylake cores, attached some extra cache and vector processing stuff, throw in various other bits and pieces, and packaged them up as Xeon CPUs codenamed Purley. In an attempt to simplify its server chip family, Chipzilla has decided to rebrand the components as Xeon Scalable Processors, assigning each a …
I note that it refers to more than 8 CPU designs being possible with a "node controller". So maybe we will get Wintel boxes that are more able to compete on scale up with the likes of Power and Sparc systems?
The -F variants contain an integrated 100Gbps Omni-Path port, not an extra UPI.
What's old is new again...
Base/bound registers to prevent one program from stepping on memory dedicated to another? I first encountered that on a CDC-6400...in 1966, so it's only taken Intel a bit over 50 years to figure it out.
Re: What's old is new again...
In fairness, the scheme offers nothing new in functional terms, because the CPU has no notion of thread as distinct from process, so the existing page protection mechanisms could always have been used to do this. What's new is that Intel reckoned that resurrecting a much more primitive scheme (costing only one register per thread) was worth it at this point in time.
No doubt the cycles of reincarnation will continue and this will soon be "legacy cruft, used by only one or two programs ever, but still needing to be implemented by every processor they ship, now and forever". Then, in about 20 years time, Intel will finally drop support for it and everyone will be aghast, ranting about the back-compat implications.
Nudge Nudge WInk WInk Say no more.
Re: Purley ?
Damn! I wanted to say that..
May also be written as khat, used as a drug in the horn of African and the Arabian peninsula.
Not mentioned the support for NVDIMM
Why not mentioned the NVDIMM support for this platform, this been delayed or not ?
Re: Not mentioned the support for NVDIMM
There was no mention of NVDIMMs by Intel in the tech materials its engineers shared with El Reg, so I guess this has been paused?
I must confess, I'm a software and CPU dude, not a storage person, so I didn't pick up on this. I've let my colleague Chris Mellor, our storage writer, know so he can follow up.
(The other Chris)
Re: Not mentioned the support for NVDIMM
That's coming in Coffee Lake, next year.
"annoyingly titled Innovation Engine: "
The "Innovation" being that it won't allow you access with a blank password?
That it wasn't bought in from another mfg without any penetration testing at all?
That this time it was designed in house and Intel reviewed the code?
What I'd have liked was a summary diagram of range of CPU/ chip. # of ports between CPUs and caches, # of ports off chip to main memory array.
As mentioned in the article, I don't see how this reclassification simplifies anything over the old classification...
The Intel Ark site - since its redesign - also goes out of its way to make it difficult to compare processor features/specifications due to its perverse layout, I actually found myself using the Wikipedia Xeon page to look up current Xeon specs the other day rather than Intel's site
It's more complicated than the previous system, which was already ridiculous. There are more levels and more models overall. This system is completely impenetrable.
> This system is completely impenetrable.
That's mission accomplished.
It's different and it takes a bit of getting used to, but there is a logic behind the new system.
Is it any coincidence that this has come along just when AMD have started looking good again? Has Intel had this in their back pocket, unmarketed, for a rainy day, depriving customers of an earlier opportunity to get this kind of thing, generally wasting their time?
Oh boy is it time for there to be some strong competition...
"Is it any coincidence that this has come along just when AMD have started looking good again?"
Depends how long this has been planned for.
Different industries and businesses have different cycles for this, usually timed around either key trade shows or conferences or the end of their financial years.
The Powerpoints may have been ready for months. However if the physical event was done in a hurry that would suggest Intel was reacting to something in a hurry, but it's not clear from the article how hastily it was set up.
Purley was announced in May 2015:
While they may have altered the launch by +/- a month or two, Purley looked like being ready late Q2/early Q3 2017
Rip out the IME and we call all sleep a bit more peacefully.
My god that new naming system, who the hell thought that was a good idea?
Early Purley Xeon vs. AMD EPYC benchmarks at Anandtech
Purley is best for very large databases and vectorisable HPC code (due to the Xeons superior L3 cache latency), while AMD EPYC is simply great for everything else and whips Intels arse on price/performance.
Mis-read the title
Came here for a conversation about Intel powered robo-monkey butlers and was disappointed. Bit of a howler on my part, now I think of it
Intel might want to glance over to the AMD server CPU site and see how easy it is to compare CPU features and performance. Chipzilla's shooting itself in both feet with the 'simplification'.