Google trumpets cloudy Skylake silicon nobody else is running Remember when PC or server-makers would breathlessly announce they'd just become the first, the very first, to get their hands on some new silicon and that doing so made them Terribly Clever? And represented enormous advantage to you, because you could buy that silicon right now instead of waiting, well, weeks for someone else …
At least on the Knights Landing Xeon Phis, AVX-512 is indeed bee's knees for floating-point performance, provided that you can keep these functional units fed. And doing this is very far from being easy: only the L1 cache has enough bandwidth to keep up with these vector units, so you need to maintain 40:1 ratio between L1 and L2 hits (and forget about going to L3 or the main memory) if you want to avoid stalls. This is just about doable for dense level-3 linear algebra (and whoever is in charge of the MKL kernels on the Xeon Phi is really, really good at getting there!). For the less structured and less memory-local code, getting AVX-512 FP unit utilization above 25% can be a real struggle, even with the excellent profiling tools Intel provides. Working with this instruction set sure brings back the memories (and the hard-earned skills) of the vector super era.
More like the fact that Xeons undergo far more stringent testing that desktop/mobile CPUs, and Google probably said "hey, we have a lot of redundancy and error detection we do so we're willing to take the risk with CPUs that aren't fully validated in order to get a bit more oomph" and Intel thought that would be fine, since they'd rather get someone to PAY them to do testing that they would otherwise have to budget power/space/cooling for themselves.
Win/win for both, and not something that enterprise customers should have a problem with, because they wouldn't want early access to a not-fully-tested Xeon.
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