back to article Get yer gnashers round 64-layer 3D NAND, beam WDC and Toshiba

Western Digital, via its acquired firm SanDisk, along with Toshiba, has started pilot production of 64-layer 3D NAND. These third generation BiCS3 chips are being fabbed at the Yokkaichi, Japan facilities, operated in a joint venture between WDC and Toshiba. Currently Samsung is shipping 48-layer 3D V-NAND chips. 64 layers is …

Layer limit?

Anyone know if there is a fundamental limit to how many layers can be stacked? Or is the only limit set by the probability of there not being a fatal defect in one layer, raised to the power of the number of layers? In which case they'll be measured in Terabits sooner rather than later.

(I recall reading in the early days of TFT displays, that defect per unit area considerations meant that nobody could ever make one bigger than 20 inches. We know how that bit of future-gazing turned out, although they do seem to get exponentially more expensive above 55 inches).

3
0

Re: Layer limit?

Stacking more than 64 layers is proving troublesome due to alignment issues with the through silicon vias (TSV) - each layer in the stack has to be perfectly aligned with the layer above and below. The more layers, the greater the difficulty of achieving the required TSV alignment. One solution is to combine two 64 layer stacks, creating a psuedo 128 layer stack - this should be relatively easy to achieve and increase yields.

3
0
Silver badge

Re: Layer limit?

There are other methods being worked on that will lead to the ability to have thousands of layers, with less processing per layer. But yes, the current method is expected to peter out at 64 or at most 96 layers, because the more layers the more troublesome connecting the I/O to all of them becomes.

1
0
Silver badge
Mushroom

Re: Layer limit?

My guess is thermal limits will start becoming the issue after a while.

Integrated Inter-layer Cooling solutions anyone?

1
0
Silver badge

Re: Layer limit?

Reading is a pretty low power activity for flash, it is the erase/write cycle that uses up a lot of power (therefore heat) So I imagine via some clever remapping (which they already do for wear leveling) they could insure the erases & writes occur in different areas to spread the heat across the whole die. You'd need a hundred thousand layers before the heat from a chip evenly spread out became an issue.

1
0
Bronze badge

At a guess it's all about probabilities and managing bad blocks and I guess some kinds of fault will render the whole device scrap or horribly unreliable even after manufacturing bad blocks are mapped out.

1
0

They test each layer before they stack them, obviously. It's not like a monolithic processor where one bad transistor can ruin the whole thing.

1
0

When it sticks out of the back of your iPhone, you're done.

2
0

These will be no thicker than the 256GB NAND stacks already shipping.

1
0

Why so small?

A quick web search shows Micron sell 2TB 2D Flash. Compared to that, what's so good about 500 Gb? Write endurance maybe, but SSDs now are good for several complete drive writes per day for years.

0
0

POST COMMENT House rules

Not a member of The Register? Create a new account here.

  • Enter your comment

  • Add an icon

Anonymous cowards cannot choose their icon

Forums

Biting the hand that feeds IT © 1998–2018