back to article Memory vendors pile on '3D' stacking standard

More memory responding faster in a smaller footprint: that's what chip vendors are hoping to achieve with the announcement of the HMC 1.0 specification. The standard, available here, sets down the specs for memory chip stacking using through-silicon vias (TSVs). In other words: individual memory dies, stacked vertically on top …


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Had to be coming sooner or later.

At present the thinnest "wire" in a chip is about 140 atoms across. Sometime within the next 10-20 years that wire will become 1 atom across, at which point all efforts to increase density by "shrinking the layout" end.

Current wafers are about 30-50x thicker than the actual active layer of the chip so there is still a lot of room to pack more data.

Handling the heat, data connections and alignment are other matters.


This is OK but not a big deal

If for some reason you need increased RAM density this might be fine but otherwise it's a solution for a problem that doesn't really exist for most consumers.

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