SRAM vs eDRAM transistor density
"Taylor said during his presentation that if IBM had stuck with SRAM-based L3 caches for the Power7+ design, it would have taken 5.4 billion transistors to etch the Power7+ chip – which would obviously have made it much larger than its 567 square millimeters." Isn't one of the trade-offs of eDRAM decreased transistor density? Poulson will for example pack 3.1B transistors in a relatively modest area of 544 mm^2. That means that some of the die size impact of the increased transistor count of using SRAM would be off-set by increased density - not that it would be a viable design option for a POWER7 derivative anyway of course.
In any case, great article. This could be a killer chip for IBM, and might even take some market share away from x86 in the form of PowerLinux. Can't wait for POWER8.