back to article 3D processor-memory mashups take center stage

A trio of devices that stack layers of compute units and memory in a single chip to boost interconnect bandwidth were presented at this week's International Solid-State Circuits Conference in San Francisco. Sharing the stage at the ISSCC's High Performance Digital session were three technologies; one prototype developed by IBM …

COMMENTS

This topic is closed for new posts.
  1. Michael H.F. Wilkinson Silver badge
    Thumb Up

    Kudos to these guys!

    The lot of them. Really interesting stuff is being made out there.

    One caveat: Igors disapprove of near threshold computing:

    "Tethting the printhiple? Thtick a bolt of lighting through it! Igorth alwayth make thythtemth that need more power!"

  2. John Smith 19 Gold badge
    Thumb Up

    To put 350W/sq. cm in perspective

    The heat shield on Apollo was spec'd at 100w/sq. cm.

    What's *really* impressive was that in the 80's Trilogy under Gene Amdahl spunked about a $1Bn trying to make multi layer wafer scale processors and failed.

    Now it's a student project.

    BTW Bell Labs devised ways to do through silicon wafers using thermal gradients to drive dopants in the *early* 80's. Making a hole with c20:1 aspect ratio is *much* more difficult (or did they build a *new* silicon layer around the vias?).

    Thumbs up for the execution in both cases.

  3. Roo
    Windows

    It's nifty stuff, but I think I'll reserve kudos for the guys who was banging away at this stuff 20 years ago. :)

    I saw some work being done on stacking a pile of DRAM dies on top of a Transputer die around 1991/1992 (albeit using gold wires/tracks on the faces of the resulting cube instead of TSVs to wire it up).

    I had a quick Google and found a paper that seemed to follow on from that work titled "An ultra compact, low-cost, complete image-processing system" submitted at the 42nd ISSCC in '95. ISBN : 0-7803-2495-1. If you succeeded in building a working V-MCM as they called it you then had the problem of keeping it cool, I'll wager the same applies today, although those 20u copper TSVs will probably help move heat around a bit better.

  4. Anonymous Coward
    Anonymous Coward

    On the subject of transputers, the third group's work looks fairly reminiscent. It would be funny to think that if after crafting those fancy tcl scripts to coerce the layout tools into fitting a 3D stack, they then had had to resort to programming it in OCCAM.

  5. Andy 70
    Thumb Up

    awesomeness

    its good we've been there before, but now making it work.

    weren't those terminator thingys based on 3D cpu's?

  6. Crisp Silver badge
    Terminator

    Re: awesomeness

    You raise a good point there. 3D chips are what got SkyNet started.

    Still, it does raise the possibility of getting your own Cameron.

  7. gorand2
    Coffee/keyboard

    Re: Re: awesomeness

    512MB sram, 256MB dram - surely there's a mistake. The dram should be more.

  8. Hsien-Hsin Lee

    Re: Re: Re: awesomeness

    It's 512KB SRAM spread out on the two logic layers.

  9. Anonymous Coward
    Anonymous Coward

    Re: Re: awesomeness

    You ought to keep up to date

    http://www.paradigmsecure.com/our_services/skynet5

  10. Scott 19
    Coat

    Thought.

    All to make porn download quicker.

  11. John Smith 19 Gold badge
    Coat

    Re: Thought.

    "All to make porn download quicker."

    Ah another generation of diligent researchers works tirelessly to permit an ever better grumble flick viewing experience.

    We will salute you, as soon as we've finished reaching for the tissues.

  12. Wang N Staines
    Thumb Up

    Well done guys!

  13. Anonymous Coward
    Joke

    Don't believe it until Apple patents it

    Don't believe it until Apple patents it

  14. Anonymous Coward
    Anonymous Coward

    IBM's "3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias": Like the other two chips, the IBM prototype routes data, clock, and power signals through its layers – what IBM calls "strata" – by means of through-silicon vias (TSVs).

    TSVs are essentaily just what they sound like: signal paths that are etched through a silicon layer and filled with a conductor. In IBM's prototype, the TSVs are copper-filled, and are about 20 micrometers (0.0008 inches) in diameter."

    "These are single parts with processor and memory closely coupled, married together in a single slab."

    thats a bit crap for 2012 ,they couldn't even bother to use a real CPU core, or even add an incredibly thin Nano-coating of alumina to the metal interconnected surfaces to double rate of heat transfer, never mind actually adding some generic cheap nano thermoelectric efficiency to the parts to recycle generated heat back into usable internal power for the ram rails, D'oh.

    next they will be saying they cant add a few "Nanoshell whispering galleries layers of Nanocrystalline-silicon (its is a great photovoltaic) to to the top surfaces so capturing and absorbing more light gradually by the silicon and so add even more free electrons to add the to whole local re-cycled power budget, to start with..... :)

  15. rajen
    Thumb Up

    What next?

    Good News. When will these designs become products?

  16. StarLady

    Prototype vs. working part?

    Please clarify: was IBM's "prototype" actually built as a 3D-IC, or did it merely emulate 3D-IC behavior?

This topic is closed for new posts.

Biting the hand that feeds IT © 1998–2018