Odd choice of name...
Intel has released some additional about its future eight-core "Poulson" Itanium processors. The Poulson chips are the first Itaniums to have a new microarchitecture and core redesign since the "McKinley" cores a decade ago. As previously reported, the processor has a total of 3.1 billion transistors and is implemented in …
This processor is the "anti-core" meaning that the majority of the design is based on making things like faster cache, faster interconnects, faster instructions etc... unlike the Core series of processors which really shine because of the huge amount of real estate allocated to instruction reordering and interpretation.
With this chip, Intel developed new power plane technologies, they developed new core communication technologies, they developed new cache sharing tech etc.... additionally, they figured out how to provide and manage a bunch of multiple API. Also, it appears their SMP methodology is relatively new for them.
Let me draw attention to the fact that as opposed to sucking a bunch of technology from the Core platform, they developed most of the new goodies in these chips FOR these chips. So, in reality, it's a huge test bed for all the good things to come in the Core series of chips in later generations. By bring what they learned here to the Core chips, they should be able to provide more cores, faster buses, more optimal instructions and such.
So, just the IP generated from this project which will be the groundwork for later Core and Xeon chips is more than enough ROI. What they make selling these actual chips is probably just gravy :)
"The one funny bit in the Poulson design are the two half-QPI links at the bottom of the chip. These were added, accoording to Riedlinger, to provide glueless interconnections for eight-socket machines. Iit would not be surprising to see them used as interconnects for linking even larger systems into a single SMP image with a modified "Boxboro" chipset from Intel or a tweaked sx3000 chipset from HP, which is used in its Integrity Superdome 2 servers."
Very strange statement as the current chip Tukwila also has the two 1/2 QPI links which add up to 1 QPI link for a total of 5. If you do the math 1 QPI link for I/O, 4 QPI links to talk to other chips then you get direct connect to 5 chips not 8. Yes it's glueless, but CPU0 has to go thru CPU6 to get to CPU7. Just look at HP's 4 wide blade wire diagram. It's borderline design flaw, but they choose not to put in the SX3000 chipset into the blades.
The Superdome2 and the SX3000 chipset is even more interesting as it only uses 3 of the QPI links as the other two are wasted.
I did not see the chip speed here but it will be 2.4GHz
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