Its about time a breakthrough was made. Last I heard, Intels roadmaps petered out at 10nm and a section marked "here be dragons".
Japanese R&D firm Unisantis says it will create and sell a new kind of "3-D" transistor that provides 10 times the computing speed of current chips. It is entering a 24-month collaborative agreement with Singapore's Institute of Microelectronics for simultaneous design work. The companies claim processor clockspeeds could …
"We'll finally be able to use MeII (read: Vista), with some of this New-Tech"
Erm, this would be M$ we're talking about?
They usually pitch their products at the processors that are just coming out and with shedloads of memory.
Whatever it is, yer ordinary mortal still won't be able to afford a machine to 'release the full potential of your new purchase'.
The chip will be manufactured in a plant in New England. Unisantis will rename themselves Unisantis Aerospace Corporation. They will call their chip the Nephesch ^9^9. It will be one micron long but will weigh more than Saturn. It will be powered by fermented "holy dung", and when it is turned on it will drive men to madness, and even death will die. And that is why I choose Paris Hilton as my avatar.
But on a tangent, The Register needs to do a follow-up on Atom Chip, the company that claimed to have made a 6ghz quantum-optical CPU and a multi-terabyte "solar memory" stick. They were reported here a couple of years ago, after an unimpressive demonstration at the 2006 CES, but they seem to have gone quiet again.
Their super-duper quantum-optical technology seemed to use 3.5mm headphone jacks and cannibalisated CD lasers:
The whole thing is fascinating, because it has the air of genuine madness about it.
NB No slight to Unisantis intended.
Did you look to the very bottom of the page? Some wonderful, almost undetectable use of PhotoShop skills on some of those images, especially the "16GB Quantum MicroSD Card and adapter"
http://atomchip.com/db4/00366/atomchip.com/_uimages/Adap16384-2.JPG (Ejected and Mounted, apparently).
This must have been some gimp's April Fool's joke, and he spent far too much time on it.
Currently the fastest working cpu is around 10Ghz and made by ibm. Intel works on a similar design and it's fastest cpu is around 8Ghz. Packing transistors in a vertical fashion is not new and the elimination of metal wires between transistors could make systems both faster, smaller and less hot. All you need is a way to put multiple layers of conducting silicium and insulating silicium dioxid on top of each other. Adding metal oxid gates to this technology could result in systems around 100 Ghz, with 1 Thz attainable in research labs. Apparently Moore's law is pretty much still works...
... everybody says that, but there are two problems to solve before: how to build the things in the first place (as it is now with only 7-8 layers, you already get enough duds ) and how to cool transistors in the centre of that structure.
@auser: silicon dioxide is on the way out, high-k dielectrics based on hafnium are all the rage these days.
The chips aren't going to be 3D! You won't have more than a single layer of transistors*. It's just that the individual transistors will have a more 3D structure. Modern CMOS transistors aren't exactly 2D either mind. *Most* of their characteristics can be modelled by assuming they have a constant cross section - but not all. Hence TCAD simulations of devices are moving from 2D to 3D. This sounds like just another variation on the FinFET idea.
Also remember kids - Moore's Law predicts the performance to cost ratio. Technologies like this (and even 'conventional' CMOS nodes approaching 32nm) may be possible but are likely to be very expensive to develop and produce.
* There isn't much point in putting multiple layers of transistors on a chip. The number of processing steps require multiplies so the cost does to (and some). It already takes hundreds of processing steps to make a CMOS wafer. The cost performance ratio doesn't really improve. There are also problems with heat dissipation, process integration, failure analysis and interconnect. The only advantage is less clock skew, but that has already been worked around by having the multiple clock domains of multi-core designs.
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