* Posts by borje

2 posts • joined 2 May 2013

Arista monster switches fluff up cloud with 1 million virty machines

borje

Impressive

Andy is in my opinion one of the best, if not the very best, HW engineers on the planet.

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AMD reveals potent parallel processing breakthrough

borje

Re: What was UMA architecture then?

To work well and with good performance, the correct page size as well as TLB structure is vital.

X86 systems today, work mostly with 4kB pages (there might be a handful of TLB-entries that can be used for huge (2MB) pages). Dividing a main memory of multiple, maybe +100 GB of memory into 4kB will be a huge overhead. It will be even worse with a combination of CPU's and GPUs.

4kB page size and 1024 TLB entries mean that you can only access 4MB of virtual memory before you need to start replacing TLB entries (reading the translation between virtual to physical memory from memory, before you can access the memory - ie you double the number of memory transactions).

SPARC and POWER today support much larger page sizes (+1GB) and this is something that needs to be done in X86 too.

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