Posts by Matt Reilly
4 posts • joined Friday 22nd June 2007 13:16 GMT
10 min charge time: what it would mean
If we're talking about driving 200 miles and charging for 10 minutes before the next
200 miles, that's a tough problem to solve:
Assume 50 mph and 20HP and PERFECT energy conversion (just for sake of argument)
that is: we're only asking 20HP out of the engine to maintain 50mph.
(200 miles / 50 mph) * 20HP * 0.7KW/HP = 56 KW-hrs * 60KW-min/KW-hr = 3360 KW-minutes
That's how much energy we would spend in a 100% efficient conversion.
Now let's replenish the energy store in 10 minutes: 3360 KW-minutes / 10 minutes = 336 KW
from the charging source.
At 110V that's 3KAmps.
That's an interesting number ;) Note that if it only took 2HP to drive us at 50mph, we'd still
be looking at 300 amps at 110V.
Posted in Intel eyes sun-powered data centers
A Step in a right direction
Kudos to Intel for harnessing solar energy.
But no grand prize. The real savings in datacenters will come when Intel acknowledges that processors developed for the desktop waste substantial power in speculative hardware, overdesign, and "engineering past the point of diminishing returns."
Fundamentally, the modern out-of-order desktop microprocessor is designed to squeeze the last tiny bit of performance out of each nanoacre of silicon, power and energy be damned. Harnessing solar energy at 1kW per square meter of array (at best) vs. machine room densities of 10kW or greater per square meter of floor space suggests some very large arrays for each of those containerized server rooms.
The best green power solution is not to waste the power in the first place.
Posted in Intel to extend chip-tech dominance
high K is good -- this isn't just about leakage
kevin: almost right, but...
The reason 'k' matters is that the ability of the gate voltage to induce inversion in the channel depends on the gate-channel capacitance. The larger the capacitance, the greater the influence between gate voltage and channel charge. Since gate-channel cap depends on k, high k for the gate oxide is desireable. Lower gate dielectric constant means lower performance transistors.
Low-k is useful in the dielectric between wires where we really need to reduce the effect of a signal on one wire upon the signal on an adjacent wire.
Filling in the numbers
Ashlee -- sorry about any confusion we may have caused on our end.
To repeat the numbers:
We've done the engineering necessary to keep the power low. We started out with an engineering budget of about 15 per node (node chip + 2 DIMMs). The node chip aimed at 10W, the rest allocated to the DIMMs. Add to that the overhead for power supply and conversion losses and you get about 18W from the wall for each node.
The 648 processor systems that we've built are measuring about 1500W from the wall running real workloads. That says that the actual node power is below our engineering budget.
So, the math again is
SC648:
6 processors per node
27 nodes per module
4 modules in a system
4 modules * 27 nodes/module = 108 nodes
108 nodes * 18 W/node = 1944W
SC5832:
6 processors per node
27 nodes per module
36 modules in a system
36 modules * 27 nodes/module = 972 nodes
972 nodes * 18 W/node = 17496W
