Re: DRAMA!!!!
"We'll have to build chips which implement better internal logic and design, rather than taking the easy route of shrinking everything..
The various chip design journals & papers are worth a read, you should read them so you don't have to take my next statement on trust. The chip design bods have zillions of neat tricks above & beyond sitting on their duffs waiting for the process guys to pull the next rabbit out of the hat.
Now back to HPC...
Essentially for 'real' HPC applications time is money - which is why they throw a lot of money at making stuff go faster. With that in mind...
1) When you start running programs on physically large systems (multi-core, multi-processor, multi-rack, multi-site etc), you will eventually want to aggregate all those results of those sub-calculations together, and that is where latency kicks you in the balls.
2) At present the lower bound on latency is set at the speed of light (C). So far we haven't found a way to increase the value of C.
3) So if we want to improve latency, but we can't increase the speed of the signals tweak the speed of light, we are left with reducing the distance travelled by the signals (ie: shrinking stuff).
The CMOS guys have actually done a very good job. Even Intel seem to have got to the point where the only real tweak they have left is upping the cache size, and at this point they seem to have run into the latency wall there too as far as CMOS goes (increasing cache size increases latency of the cache).