Re: Genuine question RISC-V / ARM
RISC-V just defines an API right ? Presumably there aren't too many innovative new Assembly Language instructions, especially in RISC, they are supposed to be simple right? (This is based on my doing a few weeks of ARM2 assembler after having learned 6502 as a kid)
Right.
There is deliberately nothing innovative in the base RISC-V instruction set. It set out to learn lessons from 30 years experience with RISC and use the best parts from RISC-I and -II, SPARC, MIPS, ARM, POWER, Alpha and others. Not from Aarch64, which was developed largely in parallel, with the basic RISC-V design being already in place when the Aarch64 ISA was published in late 2012. They *both* took many of the same lessons from experience, though Aarch64 is a bit constrained by having to run (at least up until very recent designs) on the same CPU pipeline as Aarch32, and also ARM don't seem to intend it to ever be used in the smallest devices.
The most innovative part of RISC-V so far is the just ratified Vector extension. Again, it's similar in a lot of ways to ARM's SVE. They may have both had the same influences, though it seems quite likely that SVE was influenced by the Berkeley research into vector processing. RISC-V was actually initially wanted as the scalar control processor for vector processors already in development.
So what's the massive lead of ARM over RISC-V? Obviously the silicon design of an Apple M1 is incredible, but you get this by being Apple+TSMC, not by buying an ARM license. Presumably Apple could have done the same design around a RISC-V instruction set?
Indeed Apple could have. RISC-V didn't yet have all the standardised ISA parts Apple needed at the time they started development of the M1 -- and of course not back when they made their first Aarch64 chip for the iPhone 5s released back in 2013 (and 1.5 years before ARM and their partners had 64 bit CPUs ready for the Android market e.g. Samsung Galaxy S6).
Apple wanted to get Macs on to the same ISA as iPhones and iPads, and for the moment that meant Aarch64.
Personally I think that within five years Apple will switch *everything* to an ISA they have greater control over. I don't know whether that would be RISC-V or something they design themselves.
The lead of ARM over RISC-V is mostly that they started earlier. In the case of the M1, Apple has a lot more money to spend than ARM does.
Currently shipping RISC-V cores that you can buy on an SBC (e.g. SiFive HIFive Unmatched, Starfive VisionFive v1, T-Head ICE RVB) are about 5-6 years behind ARM (e.g. Pi 3).
If you are starting to design a chip today then the RISC-V cores you can license for it e.g. SiFive P650 are about three years behind comparable ARM designs (Cortex A76).
Does ARM supply all the super-scaler / out of order pipeline / branch prediction magic we all rely on - as part of the licence design? Or is it just that there are more optomised ARM core designs out there, more people familiar with them, more tooling, more compilers etc etc ?
ARM supplies the pipeline and branch prediction if you license one of their cores. They don't if you simply license the ISA and implement your own core, as Apple does.
There is no significant difference today between the quality of gcc or LLVM compilers for ARM and RISC-V.