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* Posts by Edison Asuncion Jr.

9 posts • joined 30 Jan 2008

Intel demos 'Nehalem' chips clocked to 3.2GHz

Edison Asuncion Jr.
Happy

Phenom B3 cant even beat old Q6600, expect more from Nehalem.

we all know what current intel processors can do and how it kicks the butts of current AMD processors, including the new Phenoms who despite TLB bug fix in the B3 revision, the supposedly better hypertransport 3.0, the integrated memory controller advantage of AMD, etc... Phenom 9850 still cannot beat the good old Q6600 kentsfield in overall performance. and to remind you guys, the Q6600 is not even a Nehalem.

see Phenom, part deux: Ars reviews AMD's B3 silicon revision

http://arstechnica.com/reviews/hardware/phenom-b3-revision-review.ars/1

now that Nehalem is coming, expect greater performance since Nehalems will come with 3-channel integrated memory controller and a hypertansport-like bus which is the QuickPath Interconnect, etc.

more info on Nehalem in this Hardware Secrets article:

http://www.hardwaresecrets.com/article/535

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Intel 'Nehalem' CPU 'borrows' AMD Phenom cache plan

Edison Asuncion Jr.
Happy

both sides getting the good ideas from each other.

to make things short:

1. AMD Phenom (and Barcelona) copied Intel Core 2 Duo's true 128-bit internal datapath.

2. AMD Phenom (and Barcelona) copied Intel Core 2 Duo's Fetch Cycle - 32 bytes (256 bits) of data per clock cycle.

3. L3 Shared Cache is old Intel server technology adopted by Phenom and Barcelona.

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both sides getting the good ideas from each other.

--

now with Intel Nehalem:

1. adopted integrated memory controller concept.

2. made a hypertransport-like bus and calls it Quick-Path Interconnect.

3. native/true quad/octo-core.

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Edison Asuncion Jr.
Alert

borrowed... really?

L3 shared cache is old intel server technology adopted by the K10m architecture (Phenom and Barcelona). so did intel really borrowed this from AMD?

borrowed/copied... here are some facts;

1. The use of a true 128-bit internal datapath. On previous CPUs based on K8 microarchitecture the internal datapath was of 64 bits only. This was a problem for SSE instructions, since SSE registers, called XMM, are 128-bit long. So, when executing an instruction that manipulated a 128-bit data, this operation had to be broke down into two 64-bit operations. The new 128-bit data path makes K10 microarchitecture faster to process SSE instructions that manipulate 128-bit data compared to K8 microarchitecture.

Intel processors based on Core microarchitecture (Core 2 Duo, for example) also have 128-bit internal datapaths , while Intel processors based on Netburst microarchitecture (Pentium 4 and Pentium D) have a 64-bit internal datapaths.

AMD is calling this new feature “AMD Wide Floating Point Accelerator”.

2. The fetch unit fetches 32 bytes (256 bits) of data per clock cycle from the L1 instruction cache – this is the double CPUs based on K8 architecture could fetch per clock cycle. Intel CPUs based on Core microarchitecture, like Core 2 Duo, also fetches 32 bytes per clock cycle.

3. K10 architecture adds a shared L3 memory cache (OLD INTEL SERVER CHIP TECHNOLOGY) inside the CPU... The size of this cache will depend on the CPU model, just like what happens with the size of L2 cache.

AMD calls this approach as “Balanced Smart Cache”.

http://ocxt.multiply.com/journal/item/47/Inside_AMD_K10_Architecture.

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Bronze PSP en-route to Japan

Edison Asuncion Jr.
Happy

32MB Memory Stick Duo

how about 1 to 2GB flash instead of 32MB?

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Scientists sue Intel in Core 2 Duo clash

Edison Asuncion Jr.
Happy

@Devil, er, Intel Inside by Anonymous Coward.

Opteron (Barcelona) the better chip? so where is it?

http://blogs.zdnet.com/BTL/?p=7339

stealing techs from competitor. hmmm, the Core 2 Duo has long been using 128-bit internal data paths and Barcelona (as well as phenom) just adopted it. L3 cache? this is old intel server technology. and many more here:

http://www.hardwaresecrets.com/article/480

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AMD adjusts three-core Phenom roll-out plan, moles claim

Edison Asuncion Jr.
Happy

@Register Reader

I hope you understand the term "defect". Defects are supposed to be thrown. This case they are recycled.... errrr.. rebranded to tri-core.

But of course I would also get one if the price is right... again for budget concerns.

Cheers! 8)

PS: check the AMD website for their comparative comparison of dual-cores:

http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_9485_13041%5E13042,00.html

ever wonder... where are these intel specs 45nm, S-SSE3, and some intel lower TDP's missing, etc? why didn't AMD post the updated specs of intel when AMD post theirs down to 45W TDPs?

who's using 3DNow! ? , it's year 2008.... not 1998.

all AMD's marketing hype. 8)

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Edison Asuncion Jr.
Happy

Selling what is supposed to be trash already.

AMD quadcores with 1 defective core to be sold as tri-cores? So instead of trashing the ones with defective core, AMD would rather sell them.

Anyways there is no such thing as hard bread for me. I would still go AMD for budget solutions, and Intel for real performance.

Cheers to all. 8)

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AMD Phenom 9500 processor

Edison Asuncion Jr.
Happy

There is nothing phenomenal with Phenom.

Indeed David (AMD Athlon 64/X2) kicked Goliath (Intel - Netburst).

But now David 2.0 (Phenom) can't do that anymore and the chip giant is still on the lead... pounding poor little AMD. David 1.0 can even beat David 2.0.

Thus, there's really nothing phenomenal with the Phenom.

We all know that despite Intel processors are still on FSB and separate memory controller hub, beats AMD in overall aspects. Imagine what Intel "Nehalem" can do more with its hypertransport-like bus and integrated memory controller http://en.wikipedia.org/wiki/Nehalem_%28CPU_architecture%29 .

As for me, I will use AMD for budget reasons, and definitely go Intel for performance. Cheers to all! 8)

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Firm builds iPod speakers from packaging

Edison Asuncion Jr.
Happy

How does it sound?

So how does it sound?

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