I think Mr BLoad doesn't seem to understand the concept of the C=kA/D he's spouting.
One should be very careful about calling people Ctards when you clearly don't understand what you're talking about.
Intel are not playing around with D (thickness of the oxide).
In a 45nm process or 32nm process the oxide is already as thin as it will go. The oxide is only a couple of 10s of atoms thick. You can't go thinner, that's it, finito. If you go thinner the oxide does not behave like it does when it's thicker. At these thicknesses quantum effects kick in and electrons can jump across the oxide without it breaking down and the leakage current goes through the roof. So unfortunately D is fixed.
A or the area gets scaled down when you go from 45nm process to 32nm process etc otherwise what's the point. In order to maintain a useable capacitance then the only factor in the equation that can be adjusted is "k". Which is changed by using different materials for your dielectric. That's why they're call high "k" materials, as the "k" factor needs to be increased.
Hafnium metal gates are required because the speed of operation of the transistor is a factor of the resistance and the capacitance. Using a different metal increases speed. Increases cost too.
There are many many many papers on this stuff available from the IEEE just search. (Very technical though) I've simplified it as much as possible.