Alternative multicore model?
This isn't quite the right place to ask, but there is a question I have about future ARM directions, so if anybody (especially if from ARM) is knowledgeable, I'd be very interested.
But first off, an utter pox on people who start technical threads with questions about share prices.
So: multicore ARMs seem to use the traditional shared-memory model, which I understand takes some very fast hardware and adds a lot of complexity (and therefore a rich source of hardware bugs), and it doesn't scale too well, there being only so much memory bandwidth you can plug into a chip. Also low-level synchronisation primitives are notoriously easy to mess up without either having a lot of experience, or using formal tools for verification. Therefore would a different model based on non-shared memory be viable, perhaps something to support CSP or modern variants?
Given the relatively small size of an ARM core and its relatively small memory needs (which is I guess the main pressure towards multicore, with shared-memory following as a presumption, cos that's what all the others do) you could plonk many of these independent-memory cores on a chip hopefully very much more easily.
I guess if you've already got shared-memory core designs then perhaps you would still want to use them but perhaps graft the extra CSP-ish model on the sides. And if one's problem suits it and I'm sure many do, it would be available, which is more than can be said for any other common architecture. Fairly straightforward to add, I expect (ducks hard. Very hard).
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