Chip analyst Jim Handy of Objective Analysis took exception to several issues raised in a recent 3D NAND story, and El Reg storage desk asked him a few short questions for clarification. He provided a few short answers that did just that - and here they are. El Reg: Are there TSVs (through-silicon vias – vertical electrical …

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Tuesday 10th June 2014 09:53 GMT frank ly

Diagrams?

Simple diagrams illustrating the differences in structures would be very helpful here, or links to them.

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Tuesday 10th June 2014 10:28 GMT The last doughnut

Regular monolithic chips have vias and in reality these are through silicon vias too - they would be pretty useless otherwise.

Only the TSV your article refers to are intended to mean the sort of vias you would need to make a stack-of-chips work. Through Chip Via would have been a more accurate term, but that's not your fault.

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1. Tuesday 10th June 2014 10:49 GMT bob, mon!
  
  silicon - substrate?
  
  Could TSV be interpreted as Through-Substrate Via? Or am I misunderstanding them?
  
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  1. Tuesday 10th June 2014 11:23 GMT A Twig
    
    Re: silicon - substrate?
    
    Yes, but only when the substrate is silicon ;)
    
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2. Tuesday 10th June 2014 17:47 GMT John Smith 19
  
  "Only the TSV your article refers to are intended to mean the sort of vias you would need to make a stack-of-chips work. Through Chip Via would have been a more accurate term, but that's not your fault."
  
  Historically in the chip industry the are just called "vias." As in "You'll need some vias between metal 2 and metal 4 for the clock."
  
  Formed layers on a wafer are thin, maybe a few micrometres on a wafer 300-700 micrometres thick.
  
  In contrast a through via is the full thickness long, which gives it a huge aspect ratio relative to the usual kind.
  
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